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From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  liwei1518@gmail.com,
	zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
	 abologna@redhat.com
Subject: Re: [PATCH 6/7] target/riscv/kvm: add missing KVM CSRs
Date: Wed, 23 Apr 2025 17:28:24 +0200	[thread overview]
Message-ID: <20250423-d3ca1926d6eb9b1d273b1367@orel> (raw)
In-Reply-To: <20250417124839.1870494-7-dbarboza@ventanamicro.com>

On Thu, Apr 17, 2025 at 09:48:38AM -0300, Daniel Henrique Barboza wrote:
> We're missing scounteren and senvcfg CSRs, both already present in the
> KVM UAPI.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

The patch changed enough that it's not an r-b anymore, but it probably
should have been a reported-by in the first place anyway.

> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/kvm/kvm-cpu.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index ec74520872..a91a87b175 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -251,6 +251,11 @@ static KVMCPUConfig kvm_csr_cfgs[] = {
>      KVM_CSR_CFG("stval", stval, sizeof(target_ulong), RISCV_CSR_REG(stval)),
>      KVM_CSR_CFG("sip", mip, sizeof(uint64_t), RISCV_CSR_REG(sip)),
>      KVM_CSR_CFG("satp", satp, sizeof(target_ulong), RISCV_CSR_REG(satp)),
> +    KVM_CSR_CFG("scounteren", scounteren, sizeof(uint32_t),
> +                RISCV_CSR_REG(scounteren)),
> +    KVM_CSR_CFG("senvcfg", senvcfg, sizeof(target_ulong),
> +                RISCV_CSR_REG(senvcfg)),
> +

Extra blank here and the sizeof() stuff should go away.

>  };
>  
>  static void *kvmconfig_get_env_addr(RISCVCPU *cpu, KVMCPUConfig *csr_cfg)
> @@ -696,6 +701,8 @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env)
>      env->stval = 0;
>      env->mip = 0;
>      env->satp = 0;
> +    env->scounteren = 0;
> +    env->senvcfg = 0;
>  }
>  
>  static int kvm_riscv_get_regs_fp(CPUState *cs)
> -- 
> 2.49.0
>

Thanks,
drew


  reply	other threads:[~2025-04-23 15:28 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-17 12:48 [PATCH 0/7] target/riscv/kvm: CSR related fixes Daniel Henrique Barboza
2025-04-17 12:48 ` [PATCH 1/7] target/riscv/kvm: minor fixes/tweaks Daniel Henrique Barboza
2025-04-17 12:48 ` [PATCH 2/7] target/riscv/kvm: turn u32/u64 reg functions in macros Daniel Henrique Barboza
2025-04-17 12:48 ` [PATCH 3/7] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() in a macro Daniel Henrique Barboza
2025-04-17 12:48 ` [PATCH 4/7] target/riscv/kvm: add kvm_csr_cfgs[] Daniel Henrique Barboza
2025-04-23 15:15   ` Andrew Jones
2025-04-23 19:45     ` Daniel Henrique Barboza
2025-04-24  8:19       ` Andrew Jones
2025-04-17 12:48 ` [PATCH 5/7] target/riscv/kvm: do not read unavailable CSRs Daniel Henrique Barboza
2025-04-23 15:25   ` Andrew Jones
2025-04-24 12:36     ` Daniel Henrique Barboza
2025-04-17 12:48 ` [PATCH 6/7] target/riscv/kvm: add missing KVM CSRs Daniel Henrique Barboza
2025-04-23 15:28   ` Andrew Jones [this message]
2025-04-17 12:48 ` [PATCH 7/7] target/riscv/kvm: reset 'scounteren' with host val Daniel Henrique Barboza
2025-04-23 15:46   ` Andrew Jones
2025-04-23 18:06     ` Andrea Bolognani
2025-04-23 18:46       ` Daniel Henrique Barboza
2025-04-24  9:07     ` Daniel Henrique Barboza

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