* [PATCH v3 1/5] tests: virt: Allow changes to PPTT test table
2025-04-23 11:41 [PATCH v3 0/5] Building PPTT with root node and identical implementation flag Alireza Sanaee via
@ 2025-04-23 11:41 ` Alireza Sanaee via
2025-04-23 11:41 ` [PATCH v3 2/5] hw/acpi/aml-build: Set identical implementation flag for PPTT processor nodes Alireza Sanaee via
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Alireza Sanaee via @ 2025-04-23 11:41 UTC (permalink / raw)
To: qemu-devel
Cc: anisinha, imammedo, jonathan.cameron, linuxarm, mst,
peter.maydell, prime.zeng, shameerali.kolothum.thodi, wangyanan55,
yangyicong
From: Yicong Yang <yangyicong@hisilicon.com>
Allow changes to PPTT test table, preparing for adding identical
implementation flags support and for adding a root node for all
the system.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8bf4..e84d6c695520 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,4 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/aarch64/virt/PPTT",
+"tests/data/acpi/aarch64/virt/PPTT.acpihmatvirt",
+"tests/data/acpi/aarch64/virt/PPTT.topology",
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 2/5] hw/acpi/aml-build: Set identical implementation flag for PPTT processor nodes
2025-04-23 11:41 [PATCH v3 0/5] Building PPTT with root node and identical implementation flag Alireza Sanaee via
2025-04-23 11:41 ` [PATCH v3 1/5] tests: virt: Allow changes to PPTT test table Alireza Sanaee via
@ 2025-04-23 11:41 ` Alireza Sanaee via
2025-04-23 11:41 ` [PATCH v3 3/5] hw/acpi/aml-build: Build a root node in the PPTT table Alireza Sanaee via
` (2 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Alireza Sanaee via @ 2025-04-23 11:41 UTC (permalink / raw)
To: qemu-devel
Cc: anisinha, imammedo, jonathan.cameron, linuxarm, mst,
peter.maydell, prime.zeng, shameerali.kolothum.thodi, wangyanan55,
yangyicong
From: Yicong Yang <yangyicong@hisilicon.com>
Per ACPI 6.5 Table 5.158: Processor Structure Flags, the identical
implementation flag indicates whether all the children processors
of this node share the same identical implementation revision.
Currently Linux support parsing this field [1] and maybe used to
identify the heterogeneous platform. Since qemu only support
homogeneous emulation, set this flag for all the processor node
to indicates the facts when building the PPTT table. Node leaf
is an exception since spec says this flag should be ignored
on leaf nodes by OSPM.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/acpi/pptt.c?h=v6.11-rc1#n810
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
---
hw/acpi/aml-build.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index f8f93a9f66c8..560cee12a24b 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -2173,7 +2173,8 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
core_id = -1;
socket_offset = table_data->len - pptt_start;
build_processor_hierarchy_node(table_data,
- (1 << 0), /* Physical package */
+ (1 << 0) | /* Physical package */
+ (1 << 4), /* Identical Implementation */
0, socket_id, NULL, 0);
}
@@ -2184,7 +2185,8 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
core_id = -1;
cluster_offset = table_data->len - pptt_start;
build_processor_hierarchy_node(table_data,
- (0 << 0), /* Not a physical package */
+ (0 << 0) | /* Not a physical package */
+ (1 << 4), /* Identical Implementation */
socket_offset, cluster_id, NULL, 0);
}
} else {
@@ -2202,7 +2204,8 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
core_id = cpus->cpus[n].props.core_id;
core_offset = table_data->len - pptt_start;
build_processor_hierarchy_node(table_data,
- (0 << 0), /* Not a physical package */
+ (0 << 0) | /* Not a physical package */
+ (1 << 4), /* Identical Implementation */
cluster_offset, core_id, NULL, 0);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 3/5] hw/acpi/aml-build: Build a root node in the PPTT table
2025-04-23 11:41 [PATCH v3 0/5] Building PPTT with root node and identical implementation flag Alireza Sanaee via
2025-04-23 11:41 ` [PATCH v3 1/5] tests: virt: Allow changes to PPTT test table Alireza Sanaee via
2025-04-23 11:41 ` [PATCH v3 2/5] hw/acpi/aml-build: Set identical implementation flag for PPTT processor nodes Alireza Sanaee via
@ 2025-04-23 11:41 ` Alireza Sanaee via
2025-04-23 12:41 ` Michael S. Tsirkin
2025-04-23 11:41 ` [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of " Alireza Sanaee via
2025-04-23 11:41 ` [PATCH v3 5/5] tests: virt: Update expected ACPI tables for virt test Alireza Sanaee via
4 siblings, 1 reply; 14+ messages in thread
From: Alireza Sanaee via @ 2025-04-23 11:41 UTC (permalink / raw)
To: qemu-devel
Cc: anisinha, imammedo, jonathan.cameron, linuxarm, mst,
peter.maydell, prime.zeng, shameerali.kolothum.thodi, wangyanan55,
yangyicong
From: Yicong Yang <yangyicong@hisilicon.com>
Currently we build the PPTT starting from the socket node and each
socket will be a separate tree. For a multi-socket system it'll
be hard for the OS to know the whole system is homogeneous or not
(actually we're in the current implementation) since no parent node
to telling the identical implementation informentation. Add a
root node for indicating this.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
---
hw/acpi/aml-build.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 560cee12a24b..3010325ca423 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -2153,12 +2153,25 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
int64_t socket_id = -1, cluster_id = -1, core_id = -1;
uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
uint32_t pptt_start = table_data->len;
+ uint32_t root_offset;
int n;
AcpiTable table = { .sig = "PPTT", .rev = 2,
.oem_id = oem_id, .oem_table_id = oem_table_id };
acpi_table_begin(&table, table_data);
+ /*
+ * Build a root node for all the processor nodes. Otherwise when
+ * building a multi-socket system each socket tree are separated
+ * and will be hard for the OS like Linux to know whether the
+ * system is homogeneous.
+ */
+ root_offset = table_data->len - pptt_start;
+ build_processor_hierarchy_node(table_data,
+ (1 << 0) | /* Physical package */
+ (1 << 4), /* Identical Implementation */
+ 0, 0, NULL, 0);
+
/*
* This works with the assumption that cpus[n].props.*_id has been
* sorted from top to down levels in mc->possible_cpu_arch_ids().
@@ -2175,7 +2188,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
build_processor_hierarchy_node(table_data,
(1 << 0) | /* Physical package */
(1 << 4), /* Identical Implementation */
- 0, socket_id, NULL, 0);
+ root_offset, socket_id, NULL, 0);
}
if (mc->smp_props.clusters_supported && mc->smp_props.has_clusters) {
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 3/5] hw/acpi/aml-build: Build a root node in the PPTT table
2025-04-23 11:41 ` [PATCH v3 3/5] hw/acpi/aml-build: Build a root node in the PPTT table Alireza Sanaee via
@ 2025-04-23 12:41 ` Michael S. Tsirkin
2025-04-23 13:51 ` Yicong Yang via
0 siblings, 1 reply; 14+ messages in thread
From: Michael S. Tsirkin @ 2025-04-23 12:41 UTC (permalink / raw)
To: Alireza Sanaee
Cc: qemu-devel, anisinha, imammedo, jonathan.cameron, linuxarm,
peter.maydell, prime.zeng, shameerali.kolothum.thodi, wangyanan55,
yangyicong
On Wed, Apr 23, 2025 at 12:41:28PM +0100, Alireza Sanaee wrote:
> From: Yicong Yang <yangyicong@hisilicon.com>
>
> Currently we build the PPTT starting from the socket node and each
> socket will be a separate tree. For a multi-socket system it'll
> be hard for the OS to know the whole system is homogeneous or not
> (actually we're in the current implementation) since no parent node
> to telling the identical implementation informentation. Add a
> root node for indicating this.
>
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
so how does the topology look before and after this change?
> ---
> hw/acpi/aml-build.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 560cee12a24b..3010325ca423 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -2153,12 +2153,25 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
> int64_t socket_id = -1, cluster_id = -1, core_id = -1;
> uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
> uint32_t pptt_start = table_data->len;
> + uint32_t root_offset;
> int n;
> AcpiTable table = { .sig = "PPTT", .rev = 2,
> .oem_id = oem_id, .oem_table_id = oem_table_id };
>
> acpi_table_begin(&table, table_data);
>
> + /*
> + * Build a root node for all the processor nodes. Otherwise when
> + * building a multi-socket system each socket tree are separated
is separated?
> + * and will be hard for the OS like Linux to know whether the
> + * system is homogeneous.
> + */
> + root_offset = table_data->len - pptt_start;
> + build_processor_hierarchy_node(table_data,
> + (1 << 0) | /* Physical package */
> + (1 << 4), /* Identical Implementation */
> + 0, 0, NULL, 0);
> +
> /*
> * This works with the assumption that cpus[n].props.*_id has been
> * sorted from top to down levels in mc->possible_cpu_arch_ids().
> @@ -2175,7 +2188,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
> build_processor_hierarchy_node(table_data,
> (1 << 0) | /* Physical package */
> (1 << 4), /* Identical Implementation */
> - 0, socket_id, NULL, 0);
> + root_offset, socket_id, NULL, 0);
> }
>
> if (mc->smp_props.clusters_supported && mc->smp_props.has_clusters) {
> --
> 2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 3/5] hw/acpi/aml-build: Build a root node in the PPTT table
2025-04-23 12:41 ` Michael S. Tsirkin
@ 2025-04-23 13:51 ` Yicong Yang via
0 siblings, 0 replies; 14+ messages in thread
From: Yicong Yang via @ 2025-04-23 13:51 UTC (permalink / raw)
To: Michael S. Tsirkin, Alireza Sanaee
Cc: yangyicong, qemu-devel, anisinha, imammedo, jonathan.cameron,
linuxarm, peter.maydell, prime.zeng, shameerali.kolothum.thodi,
wangyanan55
On 2025/4/23 20:41, Michael S. Tsirkin wrote:
> On Wed, Apr 23, 2025 at 12:41:28PM +0100, Alireza Sanaee wrote:
>> From: Yicong Yang <yangyicong@hisilicon.com>
>>
>> Currently we build the PPTT starting from the socket node and each
>> socket will be a separate tree. For a multi-socket system it'll
>> be hard for the OS to know the whole system is homogeneous or not
>> (actually we're in the current implementation) since no parent node
>> to telling the identical implementation informentation. Add a
>> root node for indicating this.
>>
>> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
>
> so how does the topology look before and after this change?
>
for a 2 socket system, the PPTT processor hierarchy tree before this change will be like:
[Socket 0] [Socket 1]
^ ^
|-----------\ |-----------\
[CPU 0] ... [CPU 1] [CPU 0] ... [CPU 1]
after this change there will be a root node in the tree:
[Root Node]
^
|-------------------\
[Socket 0] [Socket 1]
^ ^
|-----------\ |-----------\
[CPU 0] ... [CPU 1] [CPU 0] ... [CPU 1]
>
>> ---
>> hw/acpi/aml-build.c | 15 ++++++++++++++-
>> 1 file changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index 560cee12a24b..3010325ca423 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -2153,12 +2153,25 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
>> int64_t socket_id = -1, cluster_id = -1, core_id = -1;
>> uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
>> uint32_t pptt_start = table_data->len;
>> + uint32_t root_offset;
>> int n;
>> AcpiTable table = { .sig = "PPTT", .rev = 2,
>> .oem_id = oem_id, .oem_table_id = oem_table_id };
>>
>> acpi_table_begin(&table, table_data);
>>
>> + /*
>> + * Build a root node for all the processor nodes. Otherwise when
>> + * building a multi-socket system each socket tree are separated
>
> is separated?
>
>> + * and will be hard for the OS like Linux to know whether the
>> + * system is homogeneous.
>> + */
>> + root_offset = table_data->len - pptt_start;
>> + build_processor_hierarchy_node(table_data,
>> + (1 << 0) | /* Physical package */
>> + (1 << 4), /* Identical Implementation */
>> + 0, 0, NULL, 0);
>> +
>> /*
>> * This works with the assumption that cpus[n].props.*_id has been
>> * sorted from top to down levels in mc->possible_cpu_arch_ids().
>> @@ -2175,7 +2188,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
>> build_processor_hierarchy_node(table_data,
>> (1 << 0) | /* Physical package */
>> (1 << 4), /* Identical Implementation */
>> - 0, socket_id, NULL, 0);
>> + root_offset, socket_id, NULL, 0);
>> }
>>
>> if (mc->smp_props.clusters_supported && mc->smp_props.has_clusters) {
>> --
>> 2.34.1
>
>
> .
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of PPTT table
2025-04-23 11:41 [PATCH v3 0/5] Building PPTT with root node and identical implementation flag Alireza Sanaee via
` (2 preceding siblings ...)
2025-04-23 11:41 ` [PATCH v3 3/5] hw/acpi/aml-build: Build a root node in the PPTT table Alireza Sanaee via
@ 2025-04-23 11:41 ` Alireza Sanaee via
2025-04-23 12:39 ` Michael S. Tsirkin
2025-04-23 11:41 ` [PATCH v3 5/5] tests: virt: Update expected ACPI tables for virt test Alireza Sanaee via
4 siblings, 1 reply; 14+ messages in thread
From: Alireza Sanaee via @ 2025-04-23 11:41 UTC (permalink / raw)
To: qemu-devel
Cc: anisinha, imammedo, jonathan.cameron, linuxarm, mst,
peter.maydell, prime.zeng, shameerali.kolothum.thodi, wangyanan55,
yangyicong
From: Yicong Yang <yangyicong@hisilicon.com>
The lastest ACPI spec 6.5 support PPTT revision 3. Update it
by handy. This is compatible with previous revision.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
---
hw/acpi/aml-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 3010325ca423..e5401dfdb1a8 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -2155,7 +2155,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
uint32_t pptt_start = table_data->len;
uint32_t root_offset;
int n;
- AcpiTable table = { .sig = "PPTT", .rev = 2,
+ AcpiTable table = { .sig = "PPTT", .rev = 3,
.oem_id = oem_id, .oem_table_id = oem_table_id };
acpi_table_begin(&table, table_data);
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of PPTT table
2025-04-23 11:41 ` [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of " Alireza Sanaee via
@ 2025-04-23 12:39 ` Michael S. Tsirkin
2025-04-23 14:15 ` Yicong Yang via
0 siblings, 1 reply; 14+ messages in thread
From: Michael S. Tsirkin @ 2025-04-23 12:39 UTC (permalink / raw)
To: Alireza Sanaee
Cc: qemu-devel, anisinha, imammedo, jonathan.cameron, linuxarm,
peter.maydell, prime.zeng, shameerali.kolothum.thodi, wangyanan55,
yangyicong
On Wed, Apr 23, 2025 at 12:41:29PM +0100, Alireza Sanaee wrote:
> From: Yicong Yang <yangyicong@hisilicon.com>
>
> The lastest ACPI spec 6.5 support PPTT revision 3. Update it
> by handy. This is compatible with previous revision.
>
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
I don't get it. Why are you updating it? Which features
from the new one are you using?
> ---
> hw/acpi/aml-build.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 3010325ca423..e5401dfdb1a8 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -2155,7 +2155,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
> uint32_t pptt_start = table_data->len;
> uint32_t root_offset;
> int n;
> - AcpiTable table = { .sig = "PPTT", .rev = 2,
> + AcpiTable table = { .sig = "PPTT", .rev = 3,
> .oem_id = oem_id, .oem_table_id = oem_table_id };
>
> acpi_table_begin(&table, table_data);
> --
> 2.34.1
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of PPTT table
2025-04-23 12:39 ` Michael S. Tsirkin
@ 2025-04-23 14:15 ` Yicong Yang via
2025-04-23 15:35 ` Michael S. Tsirkin
0 siblings, 1 reply; 14+ messages in thread
From: Yicong Yang via @ 2025-04-23 14:15 UTC (permalink / raw)
To: Michael S. Tsirkin, Alireza Sanaee
Cc: yangyicong, qemu-devel, anisinha, imammedo, jonathan.cameron,
linuxarm, peter.maydell, prime.zeng, shameerali.kolothum.thodi,
wangyanan55
On 2025/4/23 20:39, Michael S. Tsirkin wrote:
> On Wed, Apr 23, 2025 at 12:41:29PM +0100, Alireza Sanaee wrote:
>> From: Yicong Yang <yangyicong@hisilicon.com>
>>
>> The lastest ACPI spec 6.5 support PPTT revision 3. Update it
>> by handy. This is compatible with previous revision.
>>
>> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
>
>
> I don't get it. Why are you updating it? Which features
> from the new one are you using?
>
no new features for this patchset. considered updating it to the latest ACPI
spec since we're going to touch the PPTT table and tested data.
>> ---
>> hw/acpi/aml-build.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>> index 3010325ca423..e5401dfdb1a8 100644
>> --- a/hw/acpi/aml-build.c
>> +++ b/hw/acpi/aml-build.c
>> @@ -2155,7 +2155,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
>> uint32_t pptt_start = table_data->len;
>> uint32_t root_offset;
>> int n;
>> - AcpiTable table = { .sig = "PPTT", .rev = 2,
>> + AcpiTable table = { .sig = "PPTT", .rev = 3,
>> .oem_id = oem_id, .oem_table_id = oem_table_id };
>>
>> acpi_table_begin(&table, table_data);
>> --
>> 2.34.1
>
>
> .
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of PPTT table
2025-04-23 14:15 ` Yicong Yang via
@ 2025-04-23 15:35 ` Michael S. Tsirkin
2025-04-23 15:47 ` Jonathan Cameron via
0 siblings, 1 reply; 14+ messages in thread
From: Michael S. Tsirkin @ 2025-04-23 15:35 UTC (permalink / raw)
To: Yicong Yang
Cc: Alireza Sanaee, yangyicong, qemu-devel, anisinha, imammedo,
jonathan.cameron, linuxarm, peter.maydell, prime.zeng,
shameerali.kolothum.thodi, wangyanan55
On Wed, Apr 23, 2025 at 10:15:42PM +0800, Yicong Yang wrote:
> On 2025/4/23 20:39, Michael S. Tsirkin wrote:
> > On Wed, Apr 23, 2025 at 12:41:29PM +0100, Alireza Sanaee wrote:
> >> From: Yicong Yang <yangyicong@hisilicon.com>
> >>
> >> The lastest ACPI spec 6.5 support PPTT revision 3. Update it
> >> by handy. This is compatible with previous revision.
> >>
> >> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
> >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> >
> >
> > I don't get it. Why are you updating it? Which features
> > from the new one are you using?
> >
>
> no new features for this patchset. considered updating it to the latest ACPI
> spec since we're going to touch the PPTT table and tested data.
it's best to wait until there are actual features you need.
don't make changes for the sake of changes, there's always
some risk.
> >> ---
> >> hw/acpi/aml-build.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> >> index 3010325ca423..e5401dfdb1a8 100644
> >> --- a/hw/acpi/aml-build.c
> >> +++ b/hw/acpi/aml-build.c
> >> @@ -2155,7 +2155,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
> >> uint32_t pptt_start = table_data->len;
> >> uint32_t root_offset;
> >> int n;
> >> - AcpiTable table = { .sig = "PPTT", .rev = 2,
> >> + AcpiTable table = { .sig = "PPTT", .rev = 3,
> >> .oem_id = oem_id, .oem_table_id = oem_table_id };
> >>
> >> acpi_table_begin(&table, table_data);
> >> --
> >> 2.34.1
> >
> >
> > .
> >
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of PPTT table
2025-04-23 15:35 ` Michael S. Tsirkin
@ 2025-04-23 15:47 ` Jonathan Cameron via
2025-04-23 15:51 ` Michael S. Tsirkin
0 siblings, 1 reply; 14+ messages in thread
From: Jonathan Cameron via @ 2025-04-23 15:47 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Yicong Yang, Alireza Sanaee, yangyicong, qemu-devel, anisinha,
imammedo, linuxarm, peter.maydell, prime.zeng,
shameerali.kolothum.thodi, wangyanan55
On Wed, 23 Apr 2025 11:35:46 -0400
"Michael S. Tsirkin" <mst@redhat.com> wrote:
> On Wed, Apr 23, 2025 at 10:15:42PM +0800, Yicong Yang wrote:
> > On 2025/4/23 20:39, Michael S. Tsirkin wrote:
> > > On Wed, Apr 23, 2025 at 12:41:29PM +0100, Alireza Sanaee wrote:
> > >> From: Yicong Yang <yangyicong@hisilicon.com>
> > >>
> > >> The lastest ACPI spec 6.5 support PPTT revision 3. Update it
> > >> by handy. This is compatible with previous revision.
> > >>
> > >> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
> > >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > >> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> > >
> > >
> > > I don't get it. Why are you updating it? Which features
> > > from the new one are you using?
> > >
> >
> > no new features for this patchset. considered updating it to the latest ACPI
> > spec since we're going to touch the PPTT table and tested data.
>
> it's best to wait until there are actual features you need.
> don't make changes for the sake of changes, there's always
> some risk.
Once we add the cache description (Ali's other set) can we make
sure we arbitrary decide to have separate cache structures. The
earlier table version allowed sharing of the entrees in the table
which then became not allowed in the newer spec. That will smooth
the path quite a bit and is a valid way to interpret the earlier spec.
If we do that, we can bring the IDs + the version update as a
precursor to MPAM support series. I don't think we need them until
that series (which is a way off being ready to merge yet!)
Jonathan
>
> > >> ---
> > >> hw/acpi/aml-build.c | 2 +-
> > >> 1 file changed, 1 insertion(+), 1 deletion(-)
> > >>
> > >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> > >> index 3010325ca423..e5401dfdb1a8 100644
> > >> --- a/hw/acpi/aml-build.c
> > >> +++ b/hw/acpi/aml-build.c
> > >> @@ -2155,7 +2155,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
> > >> uint32_t pptt_start = table_data->len;
> > >> uint32_t root_offset;
> > >> int n;
> > >> - AcpiTable table = { .sig = "PPTT", .rev = 2,
> > >> + AcpiTable table = { .sig = "PPTT", .rev = 3,
> > >> .oem_id = oem_id, .oem_table_id = oem_table_id };
> > >>
> > >> acpi_table_begin(&table, table_data);
> > >> --
> > >> 2.34.1
> > >
> > >
> > > .
> > >
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of PPTT table
2025-04-23 15:47 ` Jonathan Cameron via
@ 2025-04-23 15:51 ` Michael S. Tsirkin
2025-04-28 11:20 ` Alireza Sanaee via
0 siblings, 1 reply; 14+ messages in thread
From: Michael S. Tsirkin @ 2025-04-23 15:51 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Yicong Yang, Alireza Sanaee, yangyicong, qemu-devel, anisinha,
imammedo, linuxarm, peter.maydell, prime.zeng,
shameerali.kolothum.thodi, wangyanan55
On Wed, Apr 23, 2025 at 04:47:20PM +0100, Jonathan Cameron wrote:
> On Wed, 23 Apr 2025 11:35:46 -0400
> "Michael S. Tsirkin" <mst@redhat.com> wrote:
>
> > On Wed, Apr 23, 2025 at 10:15:42PM +0800, Yicong Yang wrote:
> > > On 2025/4/23 20:39, Michael S. Tsirkin wrote:
> > > > On Wed, Apr 23, 2025 at 12:41:29PM +0100, Alireza Sanaee wrote:
> > > >> From: Yicong Yang <yangyicong@hisilicon.com>
> > > >>
> > > >> The lastest ACPI spec 6.5 support PPTT revision 3. Update it
> > > >> by handy. This is compatible with previous revision.
> > > >>
> > > >> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
> > > >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > >> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> > > >
> > > >
> > > > I don't get it. Why are you updating it? Which features
> > > > from the new one are you using?
> > > >
> > >
> > > no new features for this patchset. considered updating it to the latest ACPI
> > > spec since we're going to touch the PPTT table and tested data.
> >
> > it's best to wait until there are actual features you need.
> > don't make changes for the sake of changes, there's always
> > some risk.
>
> Once we add the cache description (Ali's other set) can we make
> sure we arbitrary decide to have separate cache structures. The
> earlier table version allowed sharing of the entrees in the table
> which then became not allowed in the newer spec. That will smooth
> the path quite a bit and is a valid way to interpret the earlier spec.
>
> If we do that, we can bring the IDs + the version update as a
> precursor to MPAM support series. I don't think we need them until
> that series (which is a way off being ready to merge yet!)
>
> Jonathan
Why not. Sounds like all that can be made part of Ali's patchset?
I am also ok to merge things gradually, as long as it's
clear and documented in the commit log why we are
making the change and where things are going.
> >
> > > >> ---
> > > >> hw/acpi/aml-build.c | 2 +-
> > > >> 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >>
> > > >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> > > >> index 3010325ca423..e5401dfdb1a8 100644
> > > >> --- a/hw/acpi/aml-build.c
> > > >> +++ b/hw/acpi/aml-build.c
> > > >> @@ -2155,7 +2155,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
> > > >> uint32_t pptt_start = table_data->len;
> > > >> uint32_t root_offset;
> > > >> int n;
> > > >> - AcpiTable table = { .sig = "PPTT", .rev = 2,
> > > >> + AcpiTable table = { .sig = "PPTT", .rev = 3,
> > > >> .oem_id = oem_id, .oem_table_id = oem_table_id };
> > > >>
> > > >> acpi_table_begin(&table, table_data);
> > > >> --
> > > >> 2.34.1
> > > >
> > > >
> > > > .
> > > >
> >
> >
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of PPTT table
2025-04-23 15:51 ` Michael S. Tsirkin
@ 2025-04-28 11:20 ` Alireza Sanaee via
0 siblings, 0 replies; 14+ messages in thread
From: Alireza Sanaee via @ 2025-04-28 11:20 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Jonathan Cameron, Yicong Yang, yangyicong, qemu-devel, anisinha,
imammedo, linuxarm, peter.maydell, prime.zeng,
shameerali.kolothum.thodi, wangyanan55
On Wed, 23 Apr 2025 11:51:41 -0400
"Michael S. Tsirkin" <mst@redhat.com> wrote:
Hi Michael,
> On Wed, Apr 23, 2025 at 04:47:20PM +0100, Jonathan Cameron wrote:
> > On Wed, 23 Apr 2025 11:35:46 -0400
> > "Michael S. Tsirkin" <mst@redhat.com> wrote:
> >
> > > On Wed, Apr 23, 2025 at 10:15:42PM +0800, Yicong Yang wrote:
> > > > On 2025/4/23 20:39, Michael S. Tsirkin wrote:
> > > > > On Wed, Apr 23, 2025 at 12:41:29PM +0100, Alireza Sanaee
> > > > > wrote:
> > > > >> From: Yicong Yang <yangyicong@hisilicon.com>
> > > > >>
> > > > >> The lastest ACPI spec 6.5 support PPTT revision 3. Update it
> > > > >> by handy. This is compatible with previous revision.
> > > > >>
> > > > >> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
> > > > >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > > >> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> > > > >
> > > > >
> > > > > I don't get it. Why are you updating it? Which features
> > > > > from the new one are you using?
> > > > >
> > > >
> > > > no new features for this patchset. considered updating it to
> > > > the latest ACPI spec since we're going to touch the PPTT table
> > > > and tested data.
> > >
> > > it's best to wait until there are actual features you need.
> > > don't make changes for the sake of changes, there's always
> > > some risk.
> >
> > Once we add the cache description (Ali's other set) can we make
> > sure we arbitrary decide to have separate cache structures. The
> > earlier table version allowed sharing of the entrees in the table
> > which then became not allowed in the newer spec. That will smooth
> > the path quite a bit and is a valid way to interpret the earlier
> > spec.
> >
> > If we do that, we can bring the IDs + the version update as a
> > precursor to MPAM support series. I don't think we need them until
> > that series (which is a way off being ready to merge yet!)
> >
> > Jonathan
>
> Why not. Sounds like all that can be made part of Ali's patchset?
> I am also ok to merge things gradually, as long as it's
> clear and documented in the commit log why we are
> making the change and where things are going.
>
> > >
> > > > >> ---
> > > > >> hw/acpi/aml-build.c | 2 +-
> > > > >> 1 file changed, 1 insertion(+), 1 deletion(-)
> > > > >>
> > > > >> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> > > > >> index 3010325ca423..e5401dfdb1a8 100644
> > > > >> --- a/hw/acpi/aml-build.c
> > > > >> +++ b/hw/acpi/aml-build.c
> > > > >> @@ -2155,7 +2155,7 @@ void build_pptt(GArray *table_data,
> > > > >> BIOSLinker *linker, MachineState *ms, uint32_t pptt_start =
> > > > >> table_data->len; uint32_t root_offset;
> > > > >> int n;
> > > > >> - AcpiTable table = { .sig = "PPTT", .rev = 2,
> > > > >> + AcpiTable table = { .sig = "PPTT", .rev = 3,
> > > > >> .oem_id = oem_id, .oem_table_id =
> > > > >> oem_table_id };
> > > > >> acpi_table_begin(&table, table_data);
> > > > >> --
> > > > >> 2.34.1
> > > > >
> > > > >
> > > > > .
> > > > >
> > >
> > >
>
>
For this patchset, we eventually decided to rev down for now, on
another version sent earlier. We can always rev up when it is
absolutely necessary. So it is now rev == 2.
Thanks,
Alireza
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 5/5] tests: virt: Update expected ACPI tables for virt test
2025-04-23 11:41 [PATCH v3 0/5] Building PPTT with root node and identical implementation flag Alireza Sanaee via
` (3 preceding siblings ...)
2025-04-23 11:41 ` [PATCH v3 4/5] hw/acpi/aml-build: Update the revision of " Alireza Sanaee via
@ 2025-04-23 11:41 ` Alireza Sanaee via
4 siblings, 0 replies; 14+ messages in thread
From: Alireza Sanaee via @ 2025-04-23 11:41 UTC (permalink / raw)
To: qemu-devel
Cc: anisinha, imammedo, jonathan.cameron, linuxarm, mst,
peter.maydell, prime.zeng, shameerali.kolothum.thodi, wangyanan55,
yangyicong
From: Yicong Yang <yangyicong@hisilicon.com>
Update the ACPI tables according to the acpi aml_build change, also
empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT shows
below. Only about the root node adding and identification flag set
as expected.
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20210604 (64-bit version)
* Copyright (c) 2000 - 2021 Intel Corporation
*
- * Disassembly of tests/data/acpi/aarch64/virt/PPTT, Thu Sep 26 08:54:39 2024
+ * Disassembly of /tmp/aml-QNEIU2, Thu Sep 26 08:54:39 2024
*
* ACPI Data Table [PPTT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "PPTT" [Processor Properties Topology Table]
-[004h 0004 4] Table Length : 0000004C
-[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : A8
+[004h 0004 4] Table Length : 00000060
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 26
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 1] Subtable Type : 00 [Processor Hierarchy Node]
[025h 0037 1] Length : 14
[026h 0038 2] Reserved : 0000
-[028h 0040 4] Flags (decoded below) : 00000001
+[028h 0040 4] Flags (decoded below) : 00000011
Physical package : 1
ACPI Processor ID valid : 0
Processor is a thread : 0
Node is a leaf : 0
- Identical Implementation : 0
+ Identical Implementation : 1
[02Ch 0044 4] Parent : 00000000
[030h 0048 4] ACPI Processor ID : 00000000
[034h 0052 4] Private Resource Number : 00000000
[038h 0056 1] Subtable Type : 00 [Processor Hierarchy Node]
[039h 0057 1] Length : 14
[03Ah 0058 2] Reserved : 0000
-[03Ch 0060 4] Flags (decoded below) : 0000000A
+[03Ch 0060 4] Flags (decoded below) : 00000011
+ Physical package : 1
+ ACPI Processor ID valid : 0
+ Processor is a thread : 0
+ Node is a leaf : 0
+ Identical Implementation : 1
+[040h 0064 4] Parent : 00000024
+[044h 0068 4] ACPI Processor ID : 00000000
+[048h 0072 4] Private Resource Number : 00000000
+
+[04Ch 0076 1] Subtable Type : 00 [Processor Hierarchy Node]
+[04Dh 0077 1] Length : 14
+[04Eh 0078 2] Reserved : 0000
+[050h 0080 4] Flags (decoded below) : 0000000A
Physical package : 0
ACPI Processor ID valid : 1
Processor is a thread : 0
Node is a leaf : 1
Identical Implementation : 0
-[040h 0064 4] Parent : 00000024
-[044h 0068 4] ACPI Processor ID : 00000000
-[048h 0072 4] Private Resource Number : 00000000
+[054h 0084 4] Parent : 00000038
+[058h 0088 4] ACPI Processor ID : 00000000
+[05Ch 0092 4] Private Resource Number : 00000000
-Raw Table Data: Length 76 (0x4C)
+Raw Table Data: Length 96 (0x60)
- 0000: 50 50 54 54 4C 00 00 00 02 A8 42 4F 43 48 53 20 // PPTTL.....BOCHS
+ 0000: 50 50 54 54 60 00 00 00 03 26 42 4F 43 48 53 20 // PPTT`....&BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................
- 0030: 00 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ................
- 0040: 24 00 00 00 00 00 00 00 00 00 00 00 // $...........
+ 0020: 01 00 00 00 00 14 00 00 11 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 14 00 00 11 00 00 00 // ................
+ 0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $...............
+ 0050: 0A 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8...........
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
---
tests/data/acpi/aarch64/virt/PPTT | Bin 76 -> 96 bytes
tests/data/acpi/aarch64/virt/PPTT.acpihmatvirt | Bin 156 -> 176 bytes
tests/data/acpi/aarch64/virt/PPTT.topology | Bin 336 -> 356 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
4 files changed, 3 deletions(-)
diff --git a/tests/data/acpi/aarch64/virt/PPTT b/tests/data/acpi/aarch64/virt/PPTT
index 7a1258ecf123555b24462c98ccbb76b4ac1d0c2b..cafd4ee23cb4579234b36bc1b06d1380ac8fafea 100644
GIT binary patch
literal 96
zcmWFt2nk7GU|?WYbMklg2v%^42yj*a0!E-1hz+6{L>L$ZK{PUeim9N9aRK=jNMZmJ
Cw+8_L
delta 38
kcmYfB;R*-{3GrcIU|?D?kxP!15y)bg=qSvi0%AY`0D`Lo$p8QV
diff --git a/tests/data/acpi/aarch64/virt/PPTT.acpihmatvirt b/tests/data/acpi/aarch64/virt/PPTT.acpihmatvirt
index 4eef303a5b6168c6bc3795c2e2c53f65b4c4cfd4..8d560405bc7c557867efa32fef5b579f5709d729 100644
GIT binary patch
literal 176
zcmWFt2npH1z`(%F<K*w`5v<@85#X!<1dKp25F11@h%hh+f@ov_6;nYI;{x(6aEO7;
b0?8riMHU0;EdgRCkQxvGs)LC!Lqr$=th)&T
literal 156
zcmWFt2nm_Pz`(%t&&l7}BUr&HBEVSz2pEB4AU23*5Mf{d(;zks0L8d~Y!w(EL?em8
b)g$Re76a)`0AeN}1_P+x1R#eQBEkRwWK9VH
diff --git a/tests/data/acpi/aarch64/virt/PPTT.topology b/tests/data/acpi/aarch64/virt/PPTT.topology
index 3fbcae5ff08aaf16fedf4da45e941661d79c1174..d0e5e11e90f33cbbbc231f9ad0bd48419e0fea65 100644
GIT binary patch
literal 356
zcmWFt2nk7HWME*P=H&0}5v<@85#X!<1VAAM5F11@h%hh+f@ov_6;nYI69Dopu!#Af
ziSYsX2{^>Sc7o)9c7V(S=|vU;>74__Oh60<Ky@%NW+X9~TafjF#BRXUfM}@RH$Wx}
cOdLs!6-f-H7uh_Jy&6CPHY9a0F?OgJ00?*x0RR91
literal 336
zcmWFt2nh*bWME*baq@Te2v%^42yj*a0-z8Bhz+6{L>L&rG>8oYKrs+dflv?<DrSKu
z#s}p4;1GkGi=-D>45YUMh?!vef$Csl%t&G&Cde(wdO>1GKm-gx_1*yTS+Iz)B8h>R
aAic=uf$S9l3b27BK>%tVNQ@mK!T<mOd=3Es
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index e84d6c695520..dfb8523c8bf4 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,4 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/aarch64/virt/PPTT",
-"tests/data/acpi/aarch64/virt/PPTT.acpihmatvirt",
-"tests/data/acpi/aarch64/virt/PPTT.topology",
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread