From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Pierrick Bouvier <pierrick.bouvier@linaro.org>,
Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org
Cc: "Mark Cave-Ayland" <mark.caveayland@nutanix.com>,
"Anton Johansson" <anjo@rev.ng>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common
Date: Fri, 25 Apr 2025 00:20:51 +0200 [thread overview]
Message-ID: <20250424222112.36194-1-philmd@linaro.org> (raw)
Since v4:
- Add DEFINE_MACHINE_WITH_INTERFACES (Zoltan)
- Use GPtrArray for get_valid_cpu_type (Richard)
- Define InterfaceInfo[] arrays (Richard)
- Collect R-b tags
Since v3:
- QAPI structure renamed as QemuTargetInfo
- MachineClass::get_valid_cpu_types() runtime
- target_aarch64() checking SysEmuTarget value
- Remove CONFIG_TCG #ifdef'ry in hw/arm/
Since v2:
- More comments from Pierrick addressed
- Use GList to register valid CPUs list
- Remove all TARGET_AARCH64 uses in hw/arm/
Since v1:
- Dropped unrelated / irrelevant patches
- Addressed Pierrick comments
- Added R-b tag
- Only considering machines, not CPUs.
Available here, based on my pending patch queue:
https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v5
Philippe Mathieu-Daudé (21):
qapi: Rename TargetInfo structure as QemuTargetInfo
qemu: Convert target_name() to TargetInfo API
system/vl: Filter machine list available for a particular target
binary
hw/core/null-machine: Define machine as generic QOM type
hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces
hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine
hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro
hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros
hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries
meson: Prepare to accept per-binary TargetInfo structure
implementation
config/target: Implement per-binary TargetInfo structure (ARM,
AARCH64)
hw/arm/aspeed: Build objects once
hw/arm/raspi: Build objects once
hw/core/machine: Allow dynamic registration of valid CPU types
hw/arm/virt: Register valid CPU types dynamically
hw/arm/virt: Check accelerator availability at runtime
qemu/target_info: Add %target_arch field to TargetInfo
qemu/target_info: Add target_aarch64() helper
hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64()
hw/core: Introduce MachineClass::get_default_cpu_type() helper
hw/arm/virt: Get default CPU type at runtime
MAINTAINERS | 8 ++++
meson.build | 11 +++++
qapi/machine.json | 10 ++---
include/hw/arm/machines-qom.h | 31 +++++++++++++
include/hw/boards.h | 16 ++++++-
include/hw/core/cpu.h | 2 -
include/qemu/target-info-impl.h | 31 +++++++++++++
include/qemu/target-info.h | 34 ++++++++++++++
configs/targets/aarch64-softmmu.c | 23 ++++++++++
configs/targets/arm-softmmu.c | 23 ++++++++++
cpu-target.c | 5 ---
hw/arm/aspeed.c | 31 ++++++++++---
hw/arm/b-l475e-iot01a.c | 2 +
hw/arm/bananapi_m2u.c | 3 +-
hw/arm/bcm2836.c | 4 --
hw/arm/collie.c | 2 +
hw/arm/cubieboard.c | 3 +-
hw/arm/digic_boards.c | 3 +-
hw/arm/exynos4_boards.c | 3 ++
hw/arm/fby35.c | 2 +
hw/arm/highbank.c | 3 ++
hw/arm/imx25_pdk.c | 3 +-
hw/arm/imx8mp-evk.c | 4 +-
hw/arm/integratorcp.c | 3 +-
hw/arm/kzm.c | 3 +-
hw/arm/mcimx6ul-evk.c | 4 +-
hw/arm/mcimx7d-sabre.c | 4 +-
hw/arm/microbit.c | 2 +
hw/arm/mps2-tz.c | 5 +++
hw/arm/mps2.c | 5 +++
hw/arm/mps3r.c | 2 +
hw/arm/msf2-som.c | 3 +-
hw/arm/musca.c | 3 ++
hw/arm/musicpal.c | 3 +-
hw/arm/netduino2.c | 3 +-
hw/arm/netduinoplus2.c | 3 +-
hw/arm/npcm7xx_boards.c | 6 +++
hw/arm/npcm8xx_boards.c | 2 +
hw/arm/olimex-stm32-h405.c | 3 +-
hw/arm/omap_sx1.c | 3 ++
hw/arm/orangepi.c | 3 +-
hw/arm/raspi.c | 10 +++--
hw/arm/raspi4b.c | 2 +
hw/arm/realview.c | 5 +++
hw/arm/sabrelite.c | 3 +-
hw/arm/sbsa-ref.c | 2 +
hw/arm/stellaris.c | 3 ++
hw/arm/stm32vldiscovery.c | 3 +-
hw/arm/versatilepb.c | 3 ++
hw/arm/vexpress.c | 3 ++
hw/arm/virt.c | 74 ++++++++++++++++++-------------
hw/arm/xilinx_zynq.c | 2 +
hw/arm/xlnx-versal-virt.c | 2 +
hw/arm/xlnx-zcu102.c | 2 +
hw/core/machine-qmp-cmds.c | 5 ++-
hw/core/machine.c | 36 +++++++++++++++
hw/core/null-machine.c | 20 ++++++++-
plugins/loader.c | 2 +-
system/vl.c | 7 +--
target-info-qom.c | 24 ++++++++++
target-info-stub.c | 22 +++++++++
target-info.c | 26 +++++++++++
target/arm/machine.c | 12 +++++
configs/targets/meson.build | 5 +++
hw/arm/meson.build | 12 +++--
65 files changed, 513 insertions(+), 89 deletions(-)
create mode 100644 include/hw/arm/machines-qom.h
create mode 100644 include/qemu/target-info-impl.h
create mode 100644 include/qemu/target-info.h
create mode 100644 configs/targets/aarch64-softmmu.c
create mode 100644 configs/targets/arm-softmmu.c
create mode 100644 target-info-qom.c
create mode 100644 target-info-stub.c
create mode 100644 target-info.c
create mode 100644 configs/targets/meson.build
--
2.47.1
next reply other threads:[~2025-04-24 22:22 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-24 22:20 Philippe Mathieu-Daudé [this message]
2025-04-24 22:20 ` [RFC PATCH v5 01/21] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 02/21] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 03/21] system/vl: Filter machine list available for a particular target binary Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type Philippe Mathieu-Daudé
2025-04-24 22:30 ` Pierrick Bouvier
2025-04-24 22:47 ` Philippe Mathieu-Daudé
2025-04-24 22:49 ` Pierrick Bouvier
2025-04-24 22:20 ` [RFC PATCH v5 05/21] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 06/21] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 07/21] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro Philippe Mathieu-Daudé
2025-04-24 22:44 ` Pierrick Bouvier
2025-04-24 22:20 ` [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Philippe Mathieu-Daudé
2025-04-24 22:35 ` Pierrick Bouvier
2025-04-24 22:45 ` Philippe Mathieu-Daudé
2025-04-25 0:16 ` BALATON Zoltan
2025-04-25 6:05 ` Pierrick Bouvier
2025-04-25 9:43 ` BALATON Zoltan
2025-04-25 20:05 ` Pierrick Bouvier
2025-04-25 20:29 ` BALATON Zoltan
2025-04-25 20:36 ` Pierrick Bouvier
2025-04-28 6:52 ` Philippe Mathieu-Daudé
2025-04-28 10:31 ` BALATON Zoltan
2025-04-28 16:47 ` Pierrick Bouvier
2025-04-28 18:44 ` BALATON Zoltan
2025-04-28 19:09 ` Pierrick Bouvier
2025-04-29 1:10 ` BALATON Zoltan
2025-04-29 1:21 ` Pierrick Bouvier
2025-05-01 23:35 ` BALATON Zoltan
2025-05-03 19:38 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 09/21] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 10/21] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 11/21] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 12/21] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 13/21] hw/arm/raspi: " Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 14/21] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé
2025-04-24 22:43 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé
2025-04-24 22:38 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 16/21] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé
2025-04-24 22:39 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 17/21] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 18/21] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 19/21] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 20/21] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 21/21] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
2025-04-28 3:19 ` Zhang Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250424222112.36194-1-philmd@linaro.org \
--to=philmd@linaro.org \
--cc=anjo@rev.ng \
--cc=mark.caveayland@nutanix.com \
--cc=pierrick.bouvier@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).