From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Pierrick Bouvier <pierrick.bouvier@linaro.org>,
Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org
Cc: "Mark Cave-Ayland" <mark.caveayland@nutanix.com>,
"Anton Johansson" <anjo@rev.ng>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically
Date: Fri, 25 Apr 2025 00:21:06 +0200 [thread overview]
Message-ID: <20250424222112.36194-16-philmd@linaro.org> (raw)
In-Reply-To: <20250424222112.36194-1-philmd@linaro.org>
Replace the static array returned as MachineClass::valid_cpu_types[]
by a runtime one generated by MachineClass::get_valid_cpu_types()
once the machine is created (its options being processed).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/virt.c | 59 ++++++++++++++++++++++++++++-----------------------
1 file changed, 32 insertions(+), 27 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 6185ac1046f..f29f541ea93 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3126,36 +3126,41 @@ static int virt_hvf_get_physical_address_range(MachineState *ms)
return requested_ipa_size;
}
+static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
+{
+ GPtrArray *vct = g_ptr_array_new_with_free_func(g_free);
+
+#ifdef CONFIG_TCG
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a7")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a15")));
+#ifdef TARGET_AARCH64
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a35")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a55")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a72")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a76")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a710")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("a64fx")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n1")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-n2")));
+#endif /* TARGET_AARCH64 */
+#endif /* CONFIG_TCG */
+#ifdef TARGET_AARCH64
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
+#endif /* CONFIG_KVM || CONFIG_HVF */
+#endif /* TARGET_AARCH64 */
+ g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max")));
+
+ return vct;
+}
+
static void virt_machine_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
- static const char * const valid_cpu_types[] = {
-#ifdef CONFIG_TCG
- ARM_CPU_TYPE_NAME("cortex-a7"),
- ARM_CPU_TYPE_NAME("cortex-a15"),
-#ifdef TARGET_AARCH64
- ARM_CPU_TYPE_NAME("cortex-a35"),
- ARM_CPU_TYPE_NAME("cortex-a55"),
- ARM_CPU_TYPE_NAME("cortex-a72"),
- ARM_CPU_TYPE_NAME("cortex-a76"),
- ARM_CPU_TYPE_NAME("cortex-a710"),
- ARM_CPU_TYPE_NAME("a64fx"),
- ARM_CPU_TYPE_NAME("neoverse-n1"),
- ARM_CPU_TYPE_NAME("neoverse-v1"),
- ARM_CPU_TYPE_NAME("neoverse-n2"),
-#endif /* TARGET_AARCH64 */
-#endif /* CONFIG_TCG */
-#ifdef TARGET_AARCH64
- ARM_CPU_TYPE_NAME("cortex-a53"),
- ARM_CPU_TYPE_NAME("cortex-a57"),
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
- ARM_CPU_TYPE_NAME("host"),
-#endif /* CONFIG_KVM || CONFIG_HVF */
-#endif /* TARGET_AARCH64 */
- ARM_CPU_TYPE_NAME("max"),
- NULL
- };
mc->init = machvirt_init;
/* Start with max_cpus set to 512, which is the maximum supported by KVM.
@@ -3183,7 +3188,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
#else
mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
#endif
- mc->valid_cpu_types = valid_cpu_types;
+ mc->get_valid_cpu_types = virt_get_valid_cpu_types;
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
--
2.47.1
next prev parent reply other threads:[~2025-04-24 22:24 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-24 22:20 [RFC PATCH v5 00/21] single-binary: Make hw/arm/ common Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 01/21] qapi: Rename TargetInfo structure as QemuTargetInfo Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 02/21] qemu: Convert target_name() to TargetInfo API Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 03/21] system/vl: Filter machine list available for a particular target binary Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 04/21] hw/core/null-machine: Define machine as generic QOM type Philippe Mathieu-Daudé
2025-04-24 22:30 ` Pierrick Bouvier
2025-04-24 22:47 ` Philippe Mathieu-Daudé
2025-04-24 22:49 ` Pierrick Bouvier
2025-04-24 22:20 ` [RFC PATCH v5 05/21] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 06/21] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé
2025-04-24 22:20 ` [RFC PATCH v5 07/21] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro Philippe Mathieu-Daudé
2025-04-24 22:44 ` Pierrick Bouvier
2025-04-24 22:20 ` [RFC PATCH v5 08/21] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros Philippe Mathieu-Daudé
2025-04-24 22:35 ` Pierrick Bouvier
2025-04-24 22:45 ` Philippe Mathieu-Daudé
2025-04-25 0:16 ` BALATON Zoltan
2025-04-25 6:05 ` Pierrick Bouvier
2025-04-25 9:43 ` BALATON Zoltan
2025-04-25 20:05 ` Pierrick Bouvier
2025-04-25 20:29 ` BALATON Zoltan
2025-04-25 20:36 ` Pierrick Bouvier
2025-04-28 6:52 ` Philippe Mathieu-Daudé
2025-04-28 10:31 ` BALATON Zoltan
2025-04-28 16:47 ` Pierrick Bouvier
2025-04-28 18:44 ` BALATON Zoltan
2025-04-28 19:09 ` Pierrick Bouvier
2025-04-29 1:10 ` BALATON Zoltan
2025-04-29 1:21 ` Pierrick Bouvier
2025-05-01 23:35 ` BALATON Zoltan
2025-05-03 19:38 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 09/21] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 10/21] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 11/21] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 12/21] hw/arm/aspeed: Build objects once Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 13/21] hw/arm/raspi: " Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 14/21] hw/core/machine: Allow dynamic registration of valid CPU types Philippe Mathieu-Daudé
2025-04-24 22:43 ` Pierrick Bouvier
2025-04-24 22:21 ` Philippe Mathieu-Daudé [this message]
2025-04-24 22:38 ` [RFC PATCH v5 15/21] hw/arm/virt: Register valid CPU types dynamically Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 16/21] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé
2025-04-24 22:39 ` Pierrick Bouvier
2025-04-24 22:21 ` [RFC PATCH v5 17/21] qemu/target_info: Add %target_arch field to TargetInfo Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 18/21] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 19/21] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 20/21] hw/core: Introduce MachineClass::get_default_cpu_type() helper Philippe Mathieu-Daudé
2025-04-24 22:21 ` [RFC PATCH v5 21/21] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
2025-04-28 3:19 ` Zhang Chen
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