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Fri, 25 Apr 2025 04:45:58 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::f716]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073e47307sm2135892f8f.65.2025.04.25.04.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 04:45:58 -0700 (PDT) Date: Fri, 25 Apr 2025 13:45:57 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v2 3/9] target/riscv/kvm: turn u32/u64 reg functions in macros Message-ID: <20250425-b84985838e1b75c6bf1cc189@orel> References: <20250425113705.2741457-1-dbarboza@ventanamicro.com> <20250425113705.2741457-4-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250425113705.2741457-4-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org sed s/in/into/ <<<$SUBJECT On Fri, Apr 25, 2025 at 08:36:59AM -0300, Daniel Henrique Barboza wrote: > This change is motivated by a future change w.r.t CSRs management. We > want to handle them the same way as KVM extensions, i.e. a static array > with KVMCPUConfig objs that will be read/write during init and so on. > But to do that properly we must be able to declare a static array that > hold KVM regs. > > C does not allow to init static arrays and use functions as > initializers, e.g. we can't do: > > .kvm_reg_id = kvm_riscv_reg_id_ulong(...) > > When instantiating the array. We can do that with macros though, so our > goal is turn kvm_riscv_reg_ulong() in a macro. It is cleaner to turn > every other reg_id_*() function in macros, and ulong will end up using > the macros for u32 and u64, so we'll start with them. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/kvm/kvm-cpu.c | 22 +++++++++------------- > 1 file changed, 9 insertions(+), 13 deletions(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 6ba122f360..c91ecdfe59 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -58,6 +58,12 @@ void riscv_kvm_aplic_request(void *opaque, int irq, int level) > > static bool cap_has_mp_state; > > +#define KVM_RISCV_REG_ID_U32(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U32 | \ > + type | idx) > + > +#define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 | \ > + type | idx) > + > static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, > uint64_t idx) > { > @@ -76,16 +82,6 @@ static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, > return id; > } > > -static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) > -{ > - return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; > -} > - > -static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) > -{ > - return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; > -} > - > static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) > { > uint64_t size_ctz = __builtin_ctz(size_b); > @@ -119,12 +115,12 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, > kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ > KVM_REG_RISCV_CONFIG_REG(name)) > > -#define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ > +#define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ > KVM_REG_RISCV_TIMER_REG(name)) > > -#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) > +#define RISCV_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx) > > -#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) > +#define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) > > #define RISCV_VECTOR_CSR_REG(env, name) \ > kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ > -- > 2.49.0 > Otherwise, Reviewed-by: Andrew Jones