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Fri, 25 Apr 2025 05:11:24 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::f716]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073e461bfsm2191386f8f.79.2025.04.25.05.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 05:11:24 -0700 (PDT) Date: Fri, 25 Apr 2025 14:11:23 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v2 8/9] target/riscv: widen (m|s)counteren to target_ulong Message-ID: <20250425-d3897a3163a3fb2853763a8e@orel> References: <20250425113705.2741457-1-dbarboza@ventanamicro.com> <20250425113705.2741457-9-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250425113705.2741457-9-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Apr 25, 2025 at 08:37:04AM -0300, Daniel Henrique Barboza wrote: > We want to support scounteren as a KVM CSR. The KVM UAPI defines every > CSR size as target_ulong, and our env->scounteren is fixed at 32 bits. > > The other existing cases where the property size does not match the KVM > reg size happens with uint64_t properties, like 'mstatus'. When running > a 32 bit CPU we'll write a 32 bit 'sstatus' KVM reg into the 64 bit > 'mstatus' field. As long as we're consistent, i.e. we're always > reading/writing the same words, this is ok. > > For scounteren, a KVM guest running in a 64 bit CPU will end up writing > a 64 bit reg in a 32 bit field. This will have all sort of funny side > effects in the KVM guest that we would rather avoid. > > Increase scounteren to target_ulong to allow KVM to read/write the > scounteren CSR without any surprises. 'mcounteren' is being changed to > target_ulong for consistency. > > Aside from bumping the version of the RISCVCPU vmstate no other > behavioral changes are expected. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.h | 4 ++-- > target/riscv/machine.c | 8 ++++---- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f5a60d0c52..0623c3187b 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -400,8 +400,8 @@ struct CPUArchState { > */ > bool two_stage_indirect_lookup; > > - uint32_t scounteren; > - uint32_t mcounteren; > + target_ulong scounteren; > + target_ulong mcounteren; Let's leave mcounteren a u32 and write a comment above scounteren explaining that it's supposed to be a u32 (as the spec says) but we're using a ulong instead to support KVM's get/put due to how it's defined in struct kvm_riscv_csr. > > uint32_t scountinhibit; > uint32_t mcountinhibit; > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index df2d5bad8d..4b11b203fb 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -401,8 +401,8 @@ static const VMStateDescription vmstate_ssp = { > > const VMStateDescription vmstate_riscv_cpu = { > .name = "cpu", > - .version_id = 10, > - .minimum_version_id = 10, > + .version_id = 11, > + .minimum_version_id = 11, > .post_load = riscv_cpu_post_load, > .fields = (const VMStateField[]) { > VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), > @@ -445,8 +445,8 @@ const VMStateDescription vmstate_riscv_cpu = { > VMSTATE_UINTTL(env.mtval, RISCVCPU), > VMSTATE_UINTTL(env.miselect, RISCVCPU), > VMSTATE_UINTTL(env.siselect, RISCVCPU), > - VMSTATE_UINT32(env.scounteren, RISCVCPU), > - VMSTATE_UINT32(env.mcounteren, RISCVCPU), > + VMSTATE_UINTTL(env.scounteren, RISCVCPU), > + VMSTATE_UINTTL(env.mcounteren, RISCVCPU), Since we only expect the lower 32 bits to ever be written, then do we need to make this change? > VMSTATE_UINT32(env.scountinhibit, RISCVCPU), > VMSTATE_UINT32(env.mcountinhibit, RISCVCPU), > VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0, > -- > 2.49.0 > Thanks, drew