* [PATCH v4 0/2] riscv: Add Kunminghu CPU and platform
@ 2025-04-25 12:17 Ran Wang
2025-05-20 3:26 ` Ran Wang
2025-06-17 2:37 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Ran Wang @ 2025-04-25 12:17 UTC (permalink / raw)
To: alistair23
Cc: 3543977024, palmer, alistair.francis, liwei1518, dbarboza,
zhiwei_liu, qemu-riscv, qemu-devel, Ran Wang
This serial adds Xiangshan Kunminghu CPU and its FPGA prototype
platform, which include UART, CLINT, IMSIC, and APLIC
devices.
More details can be found at
https://github.com/OpenXiangShan/XiangShan
Patches based on alistair/riscv-to-apply.next
Huang Borong (2):
target/riscv: Add BOSC's Xiangshan Kunminghu CPU
hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA
prototype
MAINTAINERS | 7 +
configs/devices/riscv64-softmmu/default.mak | 1 +
docs/system/riscv/xiangshan-kunminghu.rst | 39 ++++
docs/system/target-riscv.rst | 1 +
hw/riscv/Kconfig | 9 +
hw/riscv/meson.build | 1 +
hw/riscv/xiangshan_kmh.c | 220 ++++++++++++++++++++
include/hw/riscv/xiangshan_kmh.h | 78 +++++++
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 64 ++++++
10 files changed, 421 insertions(+)
create mode 100644 docs/system/riscv/xiangshan-kunminghu.rst
create mode 100644 hw/riscv/xiangshan_kmh.c
create mode 100644 include/hw/riscv/xiangshan_kmh.h
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4 0/2] riscv: Add Kunminghu CPU and platform
2025-04-25 12:17 [PATCH v4 0/2] riscv: Add Kunminghu CPU and platform Ran Wang
@ 2025-05-20 3:26 ` Ran Wang
2025-06-17 2:37 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Ran Wang @ 2025-05-20 3:26 UTC (permalink / raw)
To: alistair23
Cc: 3543977024, palmer, alistair.francis, liwei1518, dbarboza,
zhiwei_liu, qemu-riscv, qemu-devel, wangran
Hello Alistair,
Could you please comment?
I'd like to know if this version of patch set need any more work.
Thanks & Regards,
Ran
On 2025/4/25 20:17, Ran Wang wrote:
> This serial adds Xiangshan Kunminghu CPU and its FPGA prototype
> platform, which include UART, CLINT, IMSIC, and APLIC
> devices.
>
> More details can be found at
> https://github.com/OpenXiangShan/XiangShan
>
> Patches based on alistair/riscv-to-apply.next
>
> Huang Borong (2):
> target/riscv: Add BOSC's Xiangshan Kunminghu CPU
> hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA
> prototype
>
> MAINTAINERS | 7 +
> configs/devices/riscv64-softmmu/default.mak | 1 +
> docs/system/riscv/xiangshan-kunminghu.rst | 39 ++++
> docs/system/target-riscv.rst | 1 +
> hw/riscv/Kconfig | 9 +
> hw/riscv/meson.build | 1 +
> hw/riscv/xiangshan_kmh.c | 220 ++++++++++++++++++++
> include/hw/riscv/xiangshan_kmh.h | 78 +++++++
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 64 ++++++
> 10 files changed, 421 insertions(+)
> create mode 100644 docs/system/riscv/xiangshan-kunminghu.rst
> create mode 100644 hw/riscv/xiangshan_kmh.c
> create mode 100644 include/hw/riscv/xiangshan_kmh.h
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4 0/2] riscv: Add Kunminghu CPU and platform
2025-04-25 12:17 [PATCH v4 0/2] riscv: Add Kunminghu CPU and platform Ran Wang
2025-05-20 3:26 ` Ran Wang
@ 2025-06-17 2:37 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2025-06-17 2:37 UTC (permalink / raw)
To: Ran Wang
Cc: 3543977024, palmer, alistair.francis, liwei1518, dbarboza,
zhiwei_liu, qemu-riscv, qemu-devel
On Fri, Apr 25, 2025 at 10:18 PM Ran Wang <wangran@bosc.ac.cn> wrote:
>
> This serial adds Xiangshan Kunminghu CPU and its FPGA prototype
> platform, which include UART, CLINT, IMSIC, and APLIC
> devices.
>
> More details can be found at
> https://github.com/OpenXiangShan/XiangShan
>
> Patches based on alistair/riscv-to-apply.next
>
> Huang Borong (2):
> target/riscv: Add BOSC's Xiangshan Kunminghu CPU
> hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA
> prototype
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> MAINTAINERS | 7 +
> configs/devices/riscv64-softmmu/default.mak | 1 +
> docs/system/riscv/xiangshan-kunminghu.rst | 39 ++++
> docs/system/target-riscv.rst | 1 +
> hw/riscv/Kconfig | 9 +
> hw/riscv/meson.build | 1 +
> hw/riscv/xiangshan_kmh.c | 220 ++++++++++++++++++++
> include/hw/riscv/xiangshan_kmh.h | 78 +++++++
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 64 ++++++
> 10 files changed, 421 insertions(+)
> create mode 100644 docs/system/riscv/xiangshan-kunminghu.rst
> create mode 100644 hw/riscv/xiangshan_kmh.c
> create mode 100644 include/hw/riscv/xiangshan_kmh.h
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-05-20 3:26 ` Ran Wang
2025-06-17 2:37 ` Alistair Francis
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