[PATCH v4 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU

[Ran Wang <wangran@bosc.ac.cn>]

From: Huang Borong <3543977024@qq.com>

Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
high-performance RISC-V processor. More details can be found at:
https://github.com/OpenXiangShan/XiangShan

Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
categorized based on four RISC-V specifications: Volume I: Unprivileged
Architecture, Volume II: Privileged Architecture, AIA, and RVA23. The
extensions within each category are organized according to the chapter
order in the specifications.

Signed-off-by: Yu Hu <huyu@bosc.ac.cn>
Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
Signed-off-by: Borong Huang <3543977024@qq.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu-qom.h |  1 +
 target/riscv/cpu.c     | 64 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 65 insertions(+)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05eb393..75f4e43408 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -55,6 +55,7 @@
 #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
 #define TYPE_RISCV_CPU_TT_ASCALON       RISCV_CPU_TYPE_NAME("tt-ascalon")
 #define TYPE_RISCV_CPU_XIANGSHAN_NANHU  RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
+#define TYPE_RISCV_CPU_XIANGSHAN_KMH    RISCV_CPU_TYPE_NAME("xiangshan-kunminghu")
 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ee20bd7ca2..1fde2769bf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3171,6 +3171,70 @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .cfg.max_satp_mode = VM_1_10_SV39,
     ),
 
+    DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH, TYPE_RISCV_VENDOR_CPU,
+        .misa_mxl_max = MXL_RV64,
+        .misa_ext = RVG | RVC | RVB | RVS | RVU | RVH | RVV,
+        .priv_spec = PRIV_VERSION_1_13_0,
+
+	/*
+	 * The RISC-V Instruction Set Manual: Volume I
+	 * Unprivileged Architecture
+	 */
+	.cfg.ext_zicntr = true,
+	.cfg.ext_zihpm = true,
+	.cfg.ext_zihintntl = true,
+	.cfg.ext_zihintpause = true,
+	.cfg.ext_zimop = true,
+	.cfg.ext_zcmop = true,
+	.cfg.ext_zicond = true,
+	.cfg.ext_zawrs = true,
+	.cfg.ext_zacas = true,
+	.cfg.ext_zfh = true,
+	.cfg.ext_zfa = true,
+	.cfg.ext_zcb = true,
+	.cfg.ext_zbc = true,
+	.cfg.ext_zvfh = true,
+	.cfg.ext_zkn = true,
+	.cfg.ext_zks = true,
+	.cfg.ext_zkt = true,
+	.cfg.ext_zvbb = true,
+	.cfg.ext_zvkt = true,
+
+	/*
+	 * The RISC-V Instruction Set Manual: Volume II
+	 * Privileged Architecture
+	 */
+	.cfg.ext_smstateen = true,
+	.cfg.ext_smcsrind = true,
+	.cfg.ext_sscsrind = true,
+	.cfg.ext_svnapot = true,
+	.cfg.ext_svpbmt = true,
+	.cfg.ext_svinval = true,
+	.cfg.ext_sstc = true,
+	.cfg.ext_sscofpmf = true,
+	.cfg.ext_ssdbltrp = true,
+	.cfg.ext_ssnpm = true,
+	.cfg.ext_smnpm = true,
+	.cfg.ext_smmpm = true,
+	.cfg.ext_sspm = true,
+	.cfg.ext_supm = true,
+
+	/* The RISC-V Advanced Interrupt Architecture */
+	.cfg.ext_smaia = true,
+	.cfg.ext_ssaia = true,
+
+	/* RVA23 Profiles */
+	.cfg.ext_zicbom = true,
+	.cfg.ext_zicbop = true,
+	.cfg.ext_zicboz = true,
+	.cfg.ext_svade = true,
+
+        .cfg.mmu = true,
+        .cfg.pmp = true,
+
+        .cfg.max_satp_mode = VM_1_10_SV48,
+    ),
+
 #ifdef CONFIG_TCG
     DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
         .cfg.max_satp_mode = VM_1_10_SV57,
-- 
2.34.1