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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Subject: [PULL 126/159] tcg: Add tcg_gen_addcio_{i32,i64,tl}
Date: Fri, 25 Apr 2025 14:54:20 -0700	[thread overview]
Message-ID: <20250425215454.886111-127-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250425215454.886111-1-richard.henderson@linaro.org>

Create a function for performing an add with carry-in
and producing carry out.  The carry-out result is boolean.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg-op-common.h |  4 ++
 include/tcg/tcg-op.h        |  2 +
 tcg/tcg-op.c                | 95 +++++++++++++++++++++++++++++++++++++
 3 files changed, 101 insertions(+)

diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index 009e2778c5..b439bdb385 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -135,6 +135,8 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
                       TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
                       TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
+void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co,
+                        TCGv_i32 a, TCGv_i32 b, TCGv_i32 ci);
 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
@@ -238,6 +240,8 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
                       TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
                       TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
+void tcg_gen_addcio_i64(TCGv_i64 r, TCGv_i64 co,
+                        TCGv_i64 a, TCGv_i64 b, TCGv_i64 ci);
 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index cded92a447..59d19755e6 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -253,6 +253,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
 #define tcg_gen_movcond_tl tcg_gen_movcond_i64
 #define tcg_gen_add2_tl tcg_gen_add2_i64
 #define tcg_gen_sub2_tl tcg_gen_sub2_i64
+#define tcg_gen_addcio_tl tcg_gen_addcio_i64
 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
 #define tcg_gen_muls2_tl tcg_gen_muls2_i64
 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
@@ -371,6 +372,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
 #define tcg_gen_movcond_tl tcg_gen_movcond_i32
 #define tcg_gen_add2_tl tcg_gen_add2_i32
 #define tcg_gen_sub2_tl tcg_gen_sub2_i32
+#define tcg_gen_addcio_tl tcg_gen_addcio_i32
 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
 #define tcg_gen_muls2_tl tcg_gen_muls2_i32
 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 447b0ebacd..b0a29278ab 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1123,6 +1123,33 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
     }
 }
 
+void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co,
+                        TCGv_i32 a, TCGv_i32 b, TCGv_i32 ci)
+{
+    if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I32, 0)) {
+        TCGv_i32 t0 = tcg_temp_ebb_new_i32();
+        TCGv_i32 zero = tcg_constant_i32(0);
+        TCGv_i32 mone = tcg_constant_i32(-1);
+
+        tcg_gen_op3_i32(INDEX_op_addco, t0, ci, mone);
+        tcg_gen_op3_i32(INDEX_op_addcio, r, a, b);
+        tcg_gen_op3_i32(INDEX_op_addci, co, zero, zero);
+        tcg_temp_free_i32(t0);
+    } else {
+        TCGv_i32 t0 = tcg_temp_ebb_new_i32();
+        TCGv_i32 t1 = tcg_temp_ebb_new_i32();
+
+        tcg_gen_add_i32(t0, a, b);
+        tcg_gen_setcond_i32(TCG_COND_LTU, t1, t0, a);
+        tcg_gen_add_i32(r, t0, ci);
+        tcg_gen_setcond_i32(TCG_COND_LTU, t0, r, t0);
+        tcg_gen_or_i32(co, t0, t1);
+
+        tcg_temp_free_i32(t0);
+        tcg_temp_free_i32(t1);
+    }
+}
+
 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
                       TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh)
 {
@@ -2868,6 +2895,74 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
     }
 }
 
+void tcg_gen_addcio_i64(TCGv_i64 r, TCGv_i64 co,
+                        TCGv_i64 a, TCGv_i64 b, TCGv_i64 ci)
+{
+    if (TCG_TARGET_REG_BITS == 64) {
+        if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I64, 0)) {
+            TCGv_i64 discard = tcg_temp_ebb_new_i64();
+            TCGv_i64 zero = tcg_constant_i64(0);
+            TCGv_i64 mone = tcg_constant_i64(-1);
+
+            tcg_gen_op3_i64(INDEX_op_addco, discard, ci, mone);
+            tcg_gen_op3_i64(INDEX_op_addcio, r, a, b);
+            tcg_gen_op3_i64(INDEX_op_addci, co, zero, zero);
+            tcg_temp_free_i64(discard);
+        } else {
+            TCGv_i64 t0 = tcg_temp_ebb_new_i64();
+            TCGv_i64 t1 = tcg_temp_ebb_new_i64();
+
+            tcg_gen_add_i64(t0, a, b);
+            tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, a);
+            tcg_gen_add_i64(r, t0, ci);
+            tcg_gen_setcond_i64(TCG_COND_LTU, t0, r, t0);
+            tcg_gen_or_i64(co, t0, t1);
+
+            tcg_temp_free_i64(t0);
+            tcg_temp_free_i64(t1);
+        }
+    } else {
+        if (tcg_op_supported(INDEX_op_addci, TCG_TYPE_I32, 0)) {
+            TCGv_i32 discard = tcg_temp_ebb_new_i32();
+            TCGv_i32 zero = tcg_constant_i32(0);
+            TCGv_i32 mone = tcg_constant_i32(-1);
+
+            tcg_gen_op3_i32(INDEX_op_addco, discard, TCGV_LOW(ci), mone);
+            tcg_gen_op3_i32(INDEX_op_addcio, discard, TCGV_HIGH(ci), mone);
+            tcg_gen_op3_i32(INDEX_op_addcio, TCGV_LOW(r),
+                            TCGV_LOW(a), TCGV_LOW(b));
+            tcg_gen_op3_i32(INDEX_op_addcio, TCGV_HIGH(r),
+                            TCGV_HIGH(a), TCGV_HIGH(b));
+            tcg_gen_op3_i32(INDEX_op_addci, TCGV_LOW(co), zero, zero);
+            tcg_temp_free_i32(discard);
+        } else {
+            TCGv_i32 t0 = tcg_temp_ebb_new_i32();
+            TCGv_i32 c0 = tcg_temp_ebb_new_i32();
+            TCGv_i32 c1 = tcg_temp_ebb_new_i32();
+
+            tcg_gen_or_i32(c1, TCGV_LOW(ci), TCGV_HIGH(ci));
+            tcg_gen_setcondi_i32(TCG_COND_NE, c1, c1, 0);
+
+            tcg_gen_add_i32(t0, TCGV_LOW(a), TCGV_LOW(b));
+            tcg_gen_setcond_i32(TCG_COND_LTU, c0, t0, TCGV_LOW(a));
+            tcg_gen_add_i32(TCGV_LOW(r), t0, c1);
+            tcg_gen_setcond_i32(TCG_COND_LTU, c1, TCGV_LOW(r), c1);
+            tcg_gen_or_i32(c1, c1, c0);
+
+            tcg_gen_add_i32(t0, TCGV_HIGH(a), TCGV_HIGH(b));
+            tcg_gen_setcond_i32(TCG_COND_LTU, c0, t0, TCGV_HIGH(a));
+            tcg_gen_add_i32(TCGV_HIGH(r), t0, c1);
+            tcg_gen_setcond_i32(TCG_COND_LTU, c1, TCGV_HIGH(r), c1);
+            tcg_gen_or_i32(TCGV_LOW(co), c0, c1);
+
+            tcg_temp_free_i32(t0);
+            tcg_temp_free_i32(c0);
+            tcg_temp_free_i32(c1);
+        }
+        tcg_gen_movi_i32(TCGV_HIGH(co), 0);
+    }
+}
+
 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
                       TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
 {
-- 
2.43.0



  parent reply	other threads:[~2025-04-25 22:33 UTC|newest]

Thread overview: 162+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-25 21:52 [PULL 000/159] tcg patch queue Richard Henderson
2025-04-25 21:52 ` [PULL 001/159] tcg/loongarch64: Fix vec_val computation in tcg_target_const_match Richard Henderson
2025-04-25 21:52 ` [PULL 002/159] tcg/loongarch64: Improve constraints for TCG_CT_CONST_VCMP Richard Henderson
2025-04-25 21:52 ` [PULL 003/159] tcg/optimize: Introduce opt_insert_{before,after} Richard Henderson
2025-04-25 21:52 ` [PULL 004/159] tcg: Add TCGType to tcg_op_insert_{after,before} Richard Henderson
2025-04-25 21:52 ` [PULL 005/159] tcg: Add all_outop[] Richard Henderson
2025-04-25 21:52 ` [PULL 006/159] tcg: Use extract2 for cross-word 64-bit extract on 32-bit host Richard Henderson
2025-04-25 21:52 ` [PULL 007/159] tcg: Remove INDEX_op_ext{8,16,32}* Richard Henderson
2025-04-25 21:52 ` [PULL 008/159] tcg: Merge INDEX_op_mov_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 009/159] tcg: Convert add to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 010/159] tcg: Merge INDEX_op_add_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 011/159] tcg: Convert and to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 012/159] tcg: Merge INDEX_op_and_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 013/159] tcg/optimize: Fold andc with immediate to and Richard Henderson
2025-04-25 21:52 ` [PULL 014/159] tcg/optimize: Emit add r, r, -1 in fold_setcond_tst_pow2 Richard Henderson
2025-04-25 21:52 ` [PULL 015/159] tcg: Convert andc to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 016/159] tcg: Merge INDEX_op_andc_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 017/159] tcg: Convert or to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 018/159] tcg: Merge INDEX_op_or_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 019/159] tcg/optimize: Fold orc with immediate to or Richard Henderson
2025-04-25 21:52 ` [PULL 020/159] tcg: Convert orc to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 021/159] tcg: Merge INDEX_op_orc_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 022/159] tcg: Convert xor to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 023/159] tcg: Merge INDEX_op_xor_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 024/159] tcg/optimize: Fold eqv with immediate to xor Richard Henderson
2025-04-25 21:52 ` [PULL 025/159] tcg: Convert eqv to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 026/159] tcg: Merge INDEX_op_eqv_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 027/159] tcg: Convert nand to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 028/159] tcg: Merge INDEX_op_nand_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 029/159] tcg/loongarch64: Do not accept constant argument to nor Richard Henderson
2025-04-25 21:52 ` [PULL 030/159] tcg: Convert nor to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 031/159] tcg: Merge INDEX_op_nor_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 032/159] tcg/arm: Fix constraints for sub Richard Henderson
2025-04-25 21:52 ` [PULL 033/159] tcg: Convert sub to TCGOutOpSubtract Richard Henderson
2025-04-25 21:52 ` [PULL 034/159] tcg: Merge INDEX_op_sub_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 035/159] tcg: Convert neg to TCGOutOpUnary Richard Henderson
2025-04-25 21:52 ` [PULL 036/159] tcg: Merge INDEX_op_neg_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 037/159] tcg: Convert not to TCGOutOpUnary Richard Henderson
2025-04-25 21:52 ` [PULL 038/159] tcg: Merge INDEX_op_not_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 039/159] tcg: Convert mul to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 040/159] tcg: Merge INDEX_op_mul_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 041/159] tcg: Convert muluh to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 042/159] tcg: Merge INDEX_op_muluh_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 043/159] tcg: Convert mulsh to TCGOutOpBinary Richard Henderson
2025-04-25 21:52 ` [PULL 044/159] tcg: Merge INDEX_op_mulsh_{i32,i64} Richard Henderson
2025-04-25 21:52 ` [PULL 045/159] tcg: Convert div to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 046/159] tcg: Merge INDEX_op_div_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 047/159] tcg: Convert divu to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 048/159] tcg: Merge INDEX_op_divu_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 049/159] tcg: Convert div2 to TCGOutOpDivRem Richard Henderson
2025-04-25 21:53 ` [PULL 050/159] tcg: Merge INDEX_op_div2_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 051/159] tcg: Convert divu2 to TCGOutOpDivRem Richard Henderson
2025-04-25 21:53 ` [PULL 052/159] tcg: Merge INDEX_op_divu2_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 053/159] tcg: Convert rem to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 054/159] tcg: Merge INDEX_op_rem_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 055/159] tcg: Convert remu to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 056/159] tcg: Merge INDEX_op_remu_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 057/159] tcg: Convert shl to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 058/159] tcg: Merge INDEX_op_shl_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 059/159] tcg: Convert shr to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 060/159] tcg: Merge INDEX_op_shr_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 061/159] tcg: Convert sar to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 062/159] tcg: Merge INDEX_op_sar_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 063/159] tcg: Do not require both rotr and rotl from the backend Richard Henderson
2025-04-25 21:53 ` [PULL 064/159] tcg: Convert rotl, rotr to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 065/159] tcg: Merge INDEX_op_rot{l,r}_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 066/159] tcg: Convert clz to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 067/159] tcg: Merge INDEX_op_clz_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 068/159] tcg: Convert ctz to TCGOutOpBinary Richard Henderson
2025-04-25 21:53 ` [PULL 069/159] tcg: Merge INDEX_op_ctz_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 070/159] tcg: Convert ctpop to TCGOutOpUnary Richard Henderson
2025-04-25 21:53 ` [PULL 071/159] tcg: Merge INDEX_op_ctpop_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 072/159] tcg: Convert muls2 to TCGOutOpMul2 Richard Henderson
2025-04-25 21:53 ` [PULL 073/159] tcg: Merge INDEX_op_muls2_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 074/159] tcg: Convert mulu2 to TCGOutOpMul2 Richard Henderson
2025-04-25 21:53 ` [PULL 075/159] tcg: Merge INDEX_op_mulu2_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 076/159] tcg/loongarch64: Support negsetcond Richard Henderson
2025-04-25 21:53 ` [PULL 077/159] tcg/mips: " Richard Henderson
2025-04-25 21:53 ` [PULL 078/159] tcg/tci: " Richard Henderson
2025-04-25 21:53 ` [PULL 079/159] tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 080/159] tcg: Convert setcond, negsetcond to TCGOutOpSetcond Richard Henderson
2025-04-25 21:53 ` [PULL 081/159] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}` Richard Henderson
2025-04-25 21:53 ` [PULL 082/159] tcg: Convert brcond to TCGOutOpBrcond Richard Henderson
2025-04-25 21:53 ` [PULL 083/159] tcg: Merge INDEX_op_brcond_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 084/159] tcg: Convert movcond to TCGOutOpMovcond Richard Henderson
2025-04-25 21:53 ` [PULL 085/159] tcg: Merge INDEX_op_movcond_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 086/159] tcg/ppc: Drop fallback constant loading in tcg_out_cmp Richard Henderson
2025-04-25 21:53 ` [PULL 087/159] tcg/arm: Expand arguments to tcg_out_cmp2 Richard Henderson
2025-04-25 21:53 ` [PULL 088/159] tcg/ppc: " Richard Henderson
2025-04-25 21:53 ` [PULL 089/159] tcg: Convert brcond2_i32 to TCGOutOpBrcond2 Richard Henderson
2025-04-25 21:53 ` [PULL 090/159] tcg: Convert setcond2_i32 to TCGOutOpSetcond2 Richard Henderson
2025-04-25 21:53 ` [PULL 091/159] tcg: Convert bswap16 to TCGOutOpBswap Richard Henderson
2025-04-25 21:53 ` [PULL 092/159] tcg: Merge INDEX_op_bswap16_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 093/159] tcg: Convert bswap32 to TCGOutOpBswap Richard Henderson
2025-04-25 21:53 ` [PULL 094/159] tcg: Merge INDEX_op_bswap32_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 095/159] tcg: Convert bswap64 to TCGOutOpUnary Richard Henderson
2025-04-25 21:53 ` [PULL 096/159] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64 Richard Henderson
2025-04-25 21:53 ` [PULL 097/159] tcg: Convert extract to TCGOutOpExtract Richard Henderson
2025-04-25 21:53 ` [PULL 098/159] tcg: Merge INDEX_op_extract_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 099/159] tcg: Convert sextract to TCGOutOpExtract Richard Henderson
2025-04-25 21:53 ` [PULL 100/159] tcg: Merge INDEX_op_sextract_{i32,i64} Richard Henderson
2025-04-25 21:53 ` [PULL 101/159] tcg: Convert ext_i32_i64 to TCGOutOpUnary Richard Henderson
2025-04-25 21:53 ` [PULL 102/159] tcg: Convert extu_i32_i64 " Richard Henderson
2025-04-25 21:53 ` [PULL 103/159] tcg: Convert extrl_i64_i32 " Richard Henderson
2025-04-25 21:53 ` [PULL 104/159] tcg: Convert extrh_i64_i32 " Richard Henderson
2025-04-25 21:53 ` [PULL 105/159] tcg: Convert deposit to TCGOutOpDeposit Richard Henderson
2025-04-25 21:54 ` [PULL 106/159] tcg/aarch64: Improve deposit Richard Henderson
2025-04-25 21:54 ` [PULL 107/159] tcg: Merge INDEX_op_deposit_{i32,i64} Richard Henderson
2025-04-25 21:54 ` [PULL 108/159] tcg: Convert extract2 to TCGOutOpExtract2 Richard Henderson
2025-04-25 21:54 ` [PULL 109/159] tcg: Merge INDEX_op_extract2_{i32,i64} Richard Henderson
2025-04-25 21:54 ` [PULL 110/159] tcg: Expand fallback add2 with 32-bit operations Richard Henderson
2025-04-25 21:54 ` [PULL 111/159] tcg: Expand fallback sub2 " Richard Henderson
2025-04-25 21:54 ` [PULL 112/159] tcg: Do not default add2/sub2_i32 for 32-bit hosts Richard Henderson
2025-04-25 21:54 ` [PULL 113/159] tcg/mips: Drop support for add2/sub2 Richard Henderson
2025-04-25 21:54 ` [PULL 114/159] tcg/riscv: " Richard Henderson
2025-04-25 21:54 ` [PULL 115/159] tcg: Move i into each for loop in liveness_pass_1 Richard Henderson
2025-04-25 21:54 ` [PULL 116/159] tcg: Sink def, nb_iargs, nb_oargs loads " Richard Henderson
2025-04-25 21:54 ` [PULL 117/159] tcg: Add add/sub with carry opcodes and infrastructure Richard Henderson
2025-04-25 21:54 ` [PULL 118/159] tcg: Add TCGOutOp structures for add/sub carry opcodes Richard Henderson
2025-04-25 21:54 ` [PULL 119/159] tcg/optimize: Handle add/sub with " Richard Henderson
2025-04-25 21:54 ` [PULL 120/159] tcg/optimize: With two const operands, prefer 0 in arg1 Richard Henderson
2025-04-25 21:54 ` [PULL 121/159] tcg: Use add carry opcodes to expand add2 Richard Henderson
2025-04-25 21:54 ` [PULL 122/159] tcg: Use sub carry opcodes to expand sub2 Richard Henderson
2025-04-25 21:54 ` [PULL 123/159] tcg/i386: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-25 21:54 ` [PULL 124/159] tcg/i386: Implement add/sub carry opcodes Richard Henderson
2025-04-25 21:54 ` [PULL 125/159] tcg/i386: Special case addci r, 0, 0 Richard Henderson
2025-04-25 21:54 ` Richard Henderson [this message]
2025-04-25 21:54 ` [PULL 127/159] target/arm: Use tcg_gen_addcio_* for ADCS Richard Henderson
2025-04-25 21:54 ` [PULL 128/159] target/hppa: Use tcg_gen_addcio_i64 Richard Henderson
2025-04-25 21:54 ` [PULL 129/159] target/microblaze: Use tcg_gen_addcio_i32 Richard Henderson
2025-04-25 21:54 ` [PULL 130/159] target/openrisc: Use tcg_gen_addcio_* for ADDC Richard Henderson
2025-04-25 21:54 ` [PULL 131/159] target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF Richard Henderson
2025-04-25 21:54 ` [PULL 132/159] target/s390x: Use tcg_gen_addcio_i64 for op_addc64 Richard Henderson
2025-04-25 21:54 ` [PULL 133/159] target/sh4: Use tcg_gen_addcio_i32 for addc Richard Henderson
2025-04-25 21:54 ` [PULL 134/159] target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int Richard Henderson
2025-04-25 21:54 ` [PULL 135/159] target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC Richard Henderson
2025-04-25 21:54 ` [PULL 136/159] tcg/aarch64: Implement add/sub carry opcodes Richard Henderson
2025-04-25 21:54 ` [PULL 137/159] tcg/arm: " Richard Henderson
2025-04-25 21:54 ` [PULL 138/159] tcg/ppc: " Richard Henderson
2025-04-25 21:54 ` [PULL 139/159] tcg/s390x: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-25 21:54 ` [PULL 140/159] tcg/s390x: Add TCG_CT_CONST_N32 Richard Henderson
2025-04-25 21:54 ` [PULL 141/159] tcg/s390x: Implement add/sub carry opcodes Richard Henderson
2025-04-25 21:54 ` [PULL 142/159] tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE Richard Henderson
2025-04-25 21:54 ` [PULL 143/159] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc Richard Henderson
2025-04-25 21:54 ` [PULL 144/159] tcg/sparc64: Implement add/sub carry opcodes Richard Henderson
2025-04-25 21:54 ` [PULL 145/159] tcg/tci: " Richard Henderson
2025-04-25 21:54 ` [PULL 146/159] tcg: Remove add2/sub2 opcodes Richard Henderson
2025-04-25 21:54 ` [PULL 147/159] tcg: Formalize tcg_out_mb Richard Henderson
2025-04-25 21:54 ` [PULL 148/159] tcg: Formalize tcg_out_br Richard Henderson
2025-04-25 21:54 ` [PULL 149/159] tcg: Formalize tcg_out_goto_ptr Richard Henderson
2025-04-25 21:54 ` [PULL 150/159] tcg: Convert ld to TCGOutOpLoad Richard Henderson
2025-04-25 21:54 ` [PULL 151/159] tcg: Merge INDEX_op_ld*_{i32,i64} Richard Henderson
2025-04-25 21:54 ` [PULL 152/159] tcg: Convert st to TCGOutOpStore Richard Henderson
2025-04-25 21:54 ` [PULL 153/159] tcg: Merge INDEX_op_st*_{i32,i64} Richard Henderson
2025-04-25 21:54 ` [PULL 154/159] tcg: Stash MemOp size in TCGOP_FLAGS Richard Henderson
2025-04-25 21:54 ` [PULL 155/159] tcg: Remove INDEX_op_qemu_st8_* Richard Henderson
2025-04-25 21:54 ` [PULL 156/159] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128} Richard Henderson
2025-04-25 21:54 ` [PULL 157/159] tcg: Convert qemu_ld{2} to TCGOutOpLoad{2} Richard Henderson
2025-04-25 21:54 ` [PULL 158/159] tcg: Convert qemu_st{2} to TCGOutOpLdSt{2} Richard Henderson
2025-04-25 21:54 ` [PULL 159/159] tcg: Remove tcg_out_op Richard Henderson
2025-04-25 22:30 ` [PULL 000/159] tcg patch queue Philippe Mathieu-Daudé
2025-04-28 17:57 ` Stefan Hajnoczi

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