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Mon, 28 Apr 2025 00:34:44 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHcQ4DtFhS0dYWhwOkt0RKWG19LnC22i6e2UuEDh54TWh2cF4dqZ9Xe8sMWyjf5CS0QZ8qKCg== X-Received: by 2002:a05:6000:144c:b0:3a0:830d:ec58 with SMTP id ffacd0b85a97d-3a0830dec71mr2224129f8f.28.1745825684045; Mon, 28 Apr 2025 00:34:44 -0700 (PDT) Received: from [192.168.122.1] ([151.95.54.106]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440a536a1d1sm116822955e9.26.2025.04.28.00.34.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 00:34:43 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH v4 00/26] target/riscv: SATP mode and CPU definition overhaul Date: Mon, 28 Apr 2025 09:34:15 +0200 Message-ID: <20250428073442.315770-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This is just a rebase of v3 on top of all pending pull requests. One patch (target/riscv: do not make RISCVCPUConfig fields conditional) went away because the field was already made unconditional by commit e4610f38095 ("target/riscv: Remove ifndef CONFIG_USER_ONLY from cpu_cfg.h", 2025-04-23). Paolo Paolo Bonzini (26): hw/riscv: acpi: only create RHCT MMU entry for supported types target/riscv: assert argument to set_satp_mode_max_supported is valid target/riscv: cpu: store max SATP mode as a single integer target/riscv: update max_satp_mode based on QOM properties target/riscv: remove supported from RISCVSATPMap target/riscv: move satp_mode.{map,init} out of CPUConfig target/riscv: introduce RISCVCPUDef target/riscv: store RISCVCPUDef struct directly in the class target/riscv: merge riscv_cpu_class_init with the class_base function target/riscv: move RISCVCPUConfig fields to a header file target/riscv: include default value in cpu_cfg_fields.h.inc target/riscv: add more RISCVCPUDef fields target/riscv: convert abstract CPU classes to RISCVCPUDef target/riscv: convert profile CPU models to RISCVCPUDef target/riscv: convert bare CPU models to RISCVCPUDef target/riscv: convert dynamic CPU models to RISCVCPUDef target/riscv: convert SiFive E CPU models to RISCVCPUDef target/riscv: convert ibex CPU models to RISCVCPUDef target/riscv: convert SiFive U models to RISCVCPUDef target/riscv: th: make CSR insertion test a bit more intuitive target/riscv: generalize custom CSR functionality target/riscv: convert TT C906 to RISCVCPUDef target/riscv: convert TT Ascalon to RISCVCPUDef target/riscv: convert Ventana V1 to RISCVCPUDef target/riscv: convert Xiangshan Nanhu to RISCVCPUDef target/riscv: remove .instance_post_init target/riscv/cpu-qom.h | 2 + target/riscv/cpu.h | 42 +- target/riscv/cpu_cfg.h | 178 +---- target/riscv/cpu_cfg_fields.h.inc | 170 +++++ hw/riscv/boot.c | 2 +- hw/riscv/virt-acpi-build.c | 15 +- hw/riscv/virt.c | 5 +- target/riscv/cpu.c | 1014 +++++++++++++---------------- target/riscv/csr.c | 11 +- target/riscv/gdbstub.c | 6 +- target/riscv/kvm/kvm-cpu.c | 27 +- target/riscv/machine.c | 2 +- target/riscv/tcg/tcg-cpu.c | 13 +- target/riscv/th_csr.c | 30 +- target/riscv/translate.c | 2 +- 15 files changed, 730 insertions(+), 789 deletions(-) create mode 100644 target/riscv/cpu_cfg_fields.h.inc -- 2.49.0