From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com
Subject: [PATCH 15/26] target/riscv: convert bare CPU models to RISCVCPUDef
Date: Mon, 28 Apr 2025 09:34:30 +0200 [thread overview]
Message-ID: <20250428073442.315770-16-pbonzini@redhat.com> (raw)
In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 58 ++++++++++++++--------------------------------
1 file changed, 17 insertions(+), 41 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c07ce5ddb9b..93992be6c4d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -733,18 +733,6 @@ static void rv128_base_cpu_init(Object *obj)
}
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
-static void rv64i_bare_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- riscv_cpu_set_misa_ext(env, RVI);
-}
-
-static void rv64e_bare_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- riscv_cpu_set_misa_ext(env, RVE);
-}
-
#endif /* !TARGET_RISCV64 */
#if defined(TARGET_RISCV32) || \
@@ -837,18 +825,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
cpu->cfg.ext_zicsr = true;
cpu->cfg.pmp = true;
}
-
-static void rv32i_bare_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- riscv_cpu_set_misa_ext(env, RVI);
-}
-
-static void rv32e_bare_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- riscv_cpu_set_misa_ext(env, RVE);
-}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -3217,19 +3193,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
}), \
}
-#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \
- { \
- .name = (type_name), \
- .parent = TYPE_RISCV_BARE_CPU, \
- .instance_init = (initfn), \
- .class_data = &((const RISCVCPUDef) { \
- .misa_mxl_max = (misa_mxl_max_), \
- .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
- .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
- .cfg.max_satp_mode = -1, \
- }), \
- }
-
#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \
{ \
.name = (type_name), \
@@ -3314,8 +3277,15 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
- DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu_init),
- DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
+
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVI
+ ),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVE
+ ),
#endif
#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
@@ -3335,8 +3305,14 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
- DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init),
- DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVI
+ ),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVE
+ ),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RVA22U64),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RVA22S64),
--
2.49.0
next prev parent reply other threads:[~2025-04-28 7:40 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-28 7:34 [PATCH v4 00/26] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-04-28 7:34 ` [PATCH 01/26] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-04-28 7:34 ` [PATCH 02/26] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-04-28 7:34 ` [PATCH 03/26] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-04-28 7:34 ` [PATCH 04/26] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-04-28 7:34 ` [PATCH 05/26] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-04-28 7:34 ` [PATCH 06/26] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-04-28 7:34 ` [PATCH 07/26] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-04-28 7:34 ` [PATCH 08/26] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-04-28 11:50 ` Daniel Henrique Barboza
2025-04-28 12:17 ` Paolo Bonzini
2025-04-28 15:20 ` Philippe Mathieu-Daudé
2025-04-28 19:26 ` Paolo Bonzini
2025-04-28 14:58 ` Richard Henderson
2025-04-28 7:34 ` [PATCH 09/26] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-04-28 7:34 ` [PATCH 10/26] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-04-28 7:34 ` [PATCH 11/26] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-04-28 7:34 ` [PATCH 12/26] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-04-28 7:34 ` [PATCH 13/26] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-04-28 7:34 ` [PATCH 14/26] target/riscv: convert profile CPU models " Paolo Bonzini
2025-04-28 7:34 ` Paolo Bonzini [this message]
2025-04-28 7:34 ` [PATCH 16/26] target/riscv: convert dynamic " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 17/26] target/riscv: convert SiFive E " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 18/26] target/riscv: convert ibex " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 19/26] target/riscv: convert SiFive U " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 20/26] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-04-28 7:34 ` [PATCH 21/26] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-04-28 7:34 ` [PATCH 22/26] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-04-29 4:23 ` Joel Stanley
2025-04-28 7:34 ` [PATCH 23/26] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 24/26] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 25/26] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 26/26] target/riscv: remove .instance_post_init Paolo Bonzini
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