From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com
Subject: [PATCH 17/26] target/riscv: convert SiFive E CPU models to RISCVCPUDef
Date: Mon, 28 Apr 2025 09:34:32 +0200 [thread overview]
Message-ID: <20250428073442.315770-18-pbonzini@redhat.com> (raw)
In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 74 ++++++++++++------------------------------
2 files changed, 21 insertions(+), 54 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 4cfdb74891e..0f9be15e47b 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -44,6 +44,7 @@
#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
+#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 56f292a3616..5b4ffc285da 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -504,23 +504,6 @@ static void rv64_sifive_u_cpu_init(Object *obj)
cpu->cfg.pmp = true;
}
-static void rv64_sifive_e_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
-}
-
static void rv64_thead_c906_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -709,23 +692,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
cpu->cfg.pmp = true;
}
-static void rv32_sifive_e_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
-}
-
static void rv32_ibex_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -747,23 +713,6 @@ static void rv32_ibex_cpu_init(Object *obj)
cpu->cfg.ext_zbc = true;
cpu->cfg.ext_zbs = true;
}
-
-static void rv32_imafcu_nommu_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
-}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -3205,6 +3154,15 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
),
+ DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E, TYPE_RISCV_VENDOR_CPU,
+ .misa_ext = RVI | RVM | RVA | RVC | RVU,
+ .priv_spec = PRIV_VERSION_1_10_0,
+ .cfg.max_satp_mode = VM_1_10_MBARE,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ .cfg.pmp = true
+ ),
+
#if defined(TARGET_RISCV32) || \
(defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
@@ -3213,8 +3171,14 @@ static const TypeInfo riscv_cpu_type_infos[] = {
),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
+ .misa_mxl_max = MXL_RV32
+ ),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E34, TYPE_RISCV_CPU_SIFIVE_E,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVF, /* IMAFCU */
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
@@ -3240,7 +3204,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV64,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
+ .misa_mxl_max = MXL_RV64
+ ),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),
--
2.49.0
next prev parent reply other threads:[~2025-04-28 7:40 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-28 7:34 [PATCH v4 00/26] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-04-28 7:34 ` [PATCH 01/26] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-04-28 7:34 ` [PATCH 02/26] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-04-28 7:34 ` [PATCH 03/26] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-04-28 7:34 ` [PATCH 04/26] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-04-28 7:34 ` [PATCH 05/26] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-04-28 7:34 ` [PATCH 06/26] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-04-28 7:34 ` [PATCH 07/26] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-04-28 7:34 ` [PATCH 08/26] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-04-28 11:50 ` Daniel Henrique Barboza
2025-04-28 12:17 ` Paolo Bonzini
2025-04-28 15:20 ` Philippe Mathieu-Daudé
2025-04-28 19:26 ` Paolo Bonzini
2025-04-28 14:58 ` Richard Henderson
2025-04-28 7:34 ` [PATCH 09/26] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-04-28 7:34 ` [PATCH 10/26] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-04-28 7:34 ` [PATCH 11/26] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-04-28 7:34 ` [PATCH 12/26] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-04-28 7:34 ` [PATCH 13/26] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-04-28 7:34 ` [PATCH 14/26] target/riscv: convert profile CPU models " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 15/26] target/riscv: convert bare " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 16/26] target/riscv: convert dynamic " Paolo Bonzini
2025-04-28 7:34 ` Paolo Bonzini [this message]
2025-04-28 7:34 ` [PATCH 18/26] target/riscv: convert ibex " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 19/26] target/riscv: convert SiFive U " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 20/26] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-04-28 7:34 ` [PATCH 21/26] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-04-28 7:34 ` [PATCH 22/26] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-04-29 4:23 ` Joel Stanley
2025-04-28 7:34 ` [PATCH 23/26] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 24/26] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 25/26] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-04-28 7:34 ` [PATCH 26/26] target/riscv: remove .instance_post_init Paolo Bonzini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250428073442.315770-18-pbonzini@redhat.com \
--to=pbonzini@redhat.com \
--cc=alistair.francis@wdc.com \
--cc=dbarboza@ventanamicro.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).