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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com
Subject: [PATCH 26/26] target/riscv: remove .instance_post_init
Date: Mon, 28 Apr 2025 09:34:41 +0200	[thread overview]
Message-ID: <20250428073442.315770-27-pbonzini@redhat.com> (raw)
In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com>

Unlike other uses of .instance_post_init, accel_cpu_instance_init()
*registers* properties, and therefore must be run before
device_post_init() which sets them to their values from -global.

In order to move all registration of properties to .instance_init,
call accel_cpu_instance_init() at the end of riscv_cpu_init().

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/riscv/cpu.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e7e9e6bfe80..f1863344e8d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1084,11 +1084,6 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
     return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
 }
 
-static void riscv_cpu_post_init(Object *obj)
-{
-    accel_cpu_instance_init(CPU(obj));
-}
-
 static void riscv_cpu_init(Object *obj)
 {
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
@@ -1144,6 +1139,8 @@ static void riscv_cpu_init(Object *obj)
         riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
     }
 #endif
+
+    accel_cpu_instance_init(CPU(obj));
 }
 
 typedef struct misa_ext_info {
@@ -2886,7 +2883,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .instance_size = sizeof(RISCVCPU),
         .instance_align = __alignof(RISCVCPU),
         .instance_init = riscv_cpu_init,
-        .instance_post_init = riscv_cpu_post_init,
         .abstract = true,
         .class_size = sizeof(RISCVCPUClass),
         .class_init = riscv_cpu_common_class_init,
-- 
2.49.0



      parent reply	other threads:[~2025-04-28  7:41 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-28  7:34 [PATCH v4 00/26] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-04-28  7:34 ` [PATCH 01/26] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-04-28  7:34 ` [PATCH 02/26] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-04-28  7:34 ` [PATCH 03/26] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-04-28  7:34 ` [PATCH 04/26] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-04-28  7:34 ` [PATCH 05/26] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-04-28  7:34 ` [PATCH 06/26] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-04-28  7:34 ` [PATCH 07/26] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-04-28  7:34 ` [PATCH 08/26] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-04-28 11:50   ` Daniel Henrique Barboza
2025-04-28 12:17     ` Paolo Bonzini
2025-04-28 15:20       ` Philippe Mathieu-Daudé
2025-04-28 19:26         ` Paolo Bonzini
2025-04-28 14:58     ` Richard Henderson
2025-04-28  7:34 ` [PATCH 09/26] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-04-28  7:34 ` [PATCH 10/26] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-04-28  7:34 ` [PATCH 11/26] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-04-28  7:34 ` [PATCH 12/26] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-04-28  7:34 ` [PATCH 13/26] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-04-28  7:34 ` [PATCH 14/26] target/riscv: convert profile CPU models " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 15/26] target/riscv: convert bare " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 16/26] target/riscv: convert dynamic " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 17/26] target/riscv: convert SiFive E " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 18/26] target/riscv: convert ibex " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 19/26] target/riscv: convert SiFive U " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 20/26] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-04-28  7:34 ` [PATCH 21/26] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-04-28  7:34 ` [PATCH 22/26] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-04-29  4:23   ` Joel Stanley
2025-04-28  7:34 ` [PATCH 23/26] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 24/26] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-04-28  7:34 ` [PATCH 25/26] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-04-28  7:34 ` Paolo Bonzini [this message]

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