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Tue, 29 Apr 2025 02:02:06 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::f716]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073cbf04dsm13577028f8f.52.2025.04.29.02.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 02:02:05 -0700 (PDT) Date: Tue, 29 Apr 2025 11:02:05 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH v4 8/9] target/riscv/kvm: read/write KVM regs via env size Message-ID: <20250429-cfab3ab0131af8d6da2f0a14@orel> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> <20250428192323.84992-9-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250428192323.84992-9-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Apr 28, 2025 at 04:23:22PM -0300, Daniel Henrique Barboza wrote: > We're going to add support for scounteren in the next patch. KVM defines > as a target_ulong CSR, while QEMU defines env->scounteren as a 32 bit > field. This will cause the current code to read/write a 64 bit CSR in a > 32 bit field when running in a 64 bit CPU. > > To prevent that, change the current logic to honor the size of the QEMU > storage instead of the KVM CSR reg. > > Signed-off-by: Daniel Henrique Barboza > Suggested-by: Andrew Jones > --- > target/riscv/kvm/kvm-cpu.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 5efee8adb2..53c34b43a2 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -135,6 +135,7 @@ typedef struct KVMCPUConfig { > const char *description; > target_ulong offset; > uint64_t kvm_reg_id; > + uint32_t prop_size; > bool user_set; > bool supported; > } KVMCPUConfig; > @@ -237,6 +238,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) > > #define KVM_CSR_CFG(_name, _env_prop, reg_id) \ > {.name = _name, .offset = ENV_CSR_OFFSET(_env_prop), \ > + .prop_size = sizeof(((CPURISCVState *)0)->_env_prop), \ > .kvm_reg_id = reg_id} > > static KVMCPUConfig kvm_csr_cfgs[] = { > @@ -632,6 +634,7 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) > { > RISCVCPU *cpu = RISCV_CPU(cs); > uint64_t reg; > + uint32_t reg32; We don't need this variable. > int i, ret; > > for (i = 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { > @@ -646,9 +649,10 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) > return ret; > } > > - if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint32_t)) { > - kvm_cpu_csr_set_u32(cpu, csr_cfg, reg); > - } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint64_t)) { > + if (csr_cfg->prop_size == sizeof(uint32_t)) { > + reg32 = reg & 0xFFFF; This is masking off too many bits. We want the lower 32, not just the lower 16. > + kvm_cpu_csr_set_u32(cpu, csr_cfg, reg32); If the compiler warns when giving this function reg, then we can cast it. kvm_cpu_csr_set_u32(cpu, csr_cfg, (uint32_t)reg); otherwise we don't need to do anything special. > + } else if (csr_cfg->prop_size == sizeof(uint64_t)) { > kvm_cpu_csr_set_u64(cpu, csr_cfg, reg); > } else { > g_assert_not_reached(); > @@ -671,9 +675,9 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) > continue; > } > > - if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint32_t)) { > + if (csr_cfg->prop_size == sizeof(uint32_t)) { > reg = kvm_cpu_csr_get_u32(cpu, csr_cfg); > - } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint64_t)) { > + } else if (csr_cfg->prop_size == sizeof(uint64_t)) { > reg = kvm_cpu_csr_get_u64(cpu, csr_cfg); > } else { > g_assert_not_reached(); > -- > 2.49.0 > Thanks, drew