* [PULL v2 000/161] tcg patch queue
@ 2025-04-29 17:43 Richard Henderson
2025-04-29 17:43 ` [PULL v2 152/161] tcg: Convert st to TCGOutOpStore Richard Henderson
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Richard Henderson @ 2025-04-29 17:43 UTC (permalink / raw)
To: qemu-devel
For v2:
- Fixed a typo in patch 152 ("tcg: Convert st to TCGOutOpStore")
affecting tcg/aarch64, and was visible as a sha512-vector failure.
- Include two extra tcg/sparc64 patches.
r~
The following changes since commit 73d29ea2417b58ca55fba1aa468ba38e3607b583:
Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging (2025-04-27 12:47:23 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250429
for you to fetch changes up to 70ab4f4ed9bbe9bcfdb105681291b4695f151522:
tcg/sparc64: Implement CTPOP (2025-04-28 13:40:17 -0700)
----------------------------------------------------------------
Convert TCG backend code generators to TCGOutOp structures,
decomposing the monolithic tcg_out_op functions.
----------------------------------------------------------------
Richard Henderson (161):
tcg/loongarch64: Fix vec_val computation in tcg_target_const_match
tcg/loongarch64: Improve constraints for TCG_CT_CONST_VCMP
tcg/optimize: Introduce opt_insert_{before,after}
tcg: Add TCGType to tcg_op_insert_{after,before}
tcg: Add all_outop[]
tcg: Use extract2 for cross-word 64-bit extract on 32-bit host
tcg: Remove INDEX_op_ext{8,16,32}*
tcg: Merge INDEX_op_mov_{i32,i64}
tcg: Convert add to TCGOutOpBinary
tcg: Merge INDEX_op_add_{i32,i64}
tcg: Convert and to TCGOutOpBinary
tcg: Merge INDEX_op_and_{i32,i64}
tcg/optimize: Fold andc with immediate to and
tcg/optimize: Emit add r,r,-1 in fold_setcond_tst_pow2
tcg: Convert andc to TCGOutOpBinary
tcg: Merge INDEX_op_andc_{i32,i64}
tcg: Convert or to TCGOutOpBinary
tcg: Merge INDEX_op_or_{i32,i64}
tcg/optimize: Fold orc with immediate to or
tcg: Convert orc to TCGOutOpBinary
tcg: Merge INDEX_op_orc_{i32,i64}
tcg: Convert xor to TCGOutOpBinary
tcg: Merge INDEX_op_xor_{i32,i64}
tcg/optimize: Fold eqv with immediate to xor
tcg: Convert eqv to TCGOutOpBinary
tcg: Merge INDEX_op_eqv_{i32,i64}
tcg: Convert nand to TCGOutOpBinary
tcg: Merge INDEX_op_nand_{i32,i64}
tcg/loongarch64: Do not accept constant argument to nor
tcg: Convert nor to TCGOutOpBinary
tcg: Merge INDEX_op_nor_{i32,i64}
tcg/arm: Fix constraints for sub
tcg: Convert sub to TCGOutOpSubtract
tcg: Merge INDEX_op_sub_{i32,i64}
tcg: Convert neg to TCGOutOpUnary
tcg: Merge INDEX_op_neg_{i32,i64}
tcg: Convert not to TCGOutOpUnary
tcg: Merge INDEX_op_not_{i32,i64}
tcg: Convert mul to TCGOutOpBinary
tcg: Merge INDEX_op_mul_{i32,i64}
tcg: Convert muluh to TCGOutOpBinary
tcg: Merge INDEX_op_muluh_{i32,i64}
tcg: Convert mulsh to TCGOutOpBinary
tcg: Merge INDEX_op_mulsh_{i32,i64}
tcg: Convert div to TCGOutOpBinary
tcg: Merge INDEX_op_div_{i32,i64}
tcg: Convert divu to TCGOutOpBinary
tcg: Merge INDEX_op_divu_{i32,i64}
tcg: Convert div2 to TCGOutOpDivRem
tcg: Merge INDEX_op_div2_{i32,i64}
tcg: Convert divu2 to TCGOutOpDivRem
tcg: Merge INDEX_op_divu2_{i32,i64}
tcg: Convert rem to TCGOutOpBinary
tcg: Merge INDEX_op_rem_{i32,i64}
tcg: Convert remu to TCGOutOpBinary
tcg: Merge INDEX_op_remu_{i32,i64}
tcg: Convert shl to TCGOutOpBinary
tcg: Merge INDEX_op_shl_{i32,i64}
tcg: Convert shr to TCGOutOpBinary
tcg: Merge INDEX_op_shr_{i32,i64}
tcg: Convert sar to TCGOutOpBinary
tcg: Merge INDEX_op_sar_{i32,i64}
tcg: Do not require both rotr and rotl from the backend
tcg: Convert rotl, rotr to TCGOutOpBinary
tcg: Merge INDEX_op_rot{l,r}_{i32,i64}
tcg: Convert clz to TCGOutOpBinary
tcg: Merge INDEX_op_clz_{i32,i64}
tcg: Convert ctz to TCGOutOpBinary
tcg: Merge INDEX_op_ctz_{i32,i64}
tcg: Convert ctpop to TCGOutOpUnary
tcg: Merge INDEX_op_ctpop_{i32,i64}
tcg: Convert muls2 to TCGOutOpMul2
tcg: Merge INDEX_op_muls2_{i32,i64}
tcg: Convert mulu2 to TCGOutOpMul2
tcg: Merge INDEX_op_mulu2_{i32,i64}
tcg/loongarch64: Support negsetcond
tcg/mips: Support negsetcond
tcg/tci: Support negsetcond
tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64}
tcg: Convert setcond, negsetcond to TCGOutOpSetcond
tcg: Merge INDEX_op_{neg}setcond_{i32,i64}`
tcg: Convert brcond to TCGOutOpBrcond
tcg: Merge INDEX_op_brcond_{i32,i64}
tcg: Convert movcond to TCGOutOpMovcond
tcg: Merge INDEX_op_movcond_{i32,i64}
tcg/ppc: Drop fallback constant loading in tcg_out_cmp
tcg/arm: Expand arguments to tcg_out_cmp2
tcg/ppc: Expand arguments to tcg_out_cmp2
tcg: Convert brcond2_i32 to TCGOutOpBrcond2
tcg: Convert setcond2_i32 to TCGOutOpSetcond2
tcg: Convert bswap16 to TCGOutOpBswap
tcg: Merge INDEX_op_bswap16_{i32,i64}
tcg: Convert bswap32 to TCGOutOpBswap
tcg: Merge INDEX_op_bswap32_{i32,i64}
tcg: Convert bswap64 to TCGOutOpUnary
tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64
tcg: Convert extract to TCGOutOpExtract
tcg: Merge INDEX_op_extract_{i32,i64}
tcg: Convert sextract to TCGOutOpExtract
tcg: Merge INDEX_op_sextract_{i32,i64}
tcg: Convert ext_i32_i64 to TCGOutOpUnary
tcg: Convert extu_i32_i64 to TCGOutOpUnary
tcg: Convert extrl_i64_i32 to TCGOutOpUnary
tcg: Convert extrh_i64_i32 to TCGOutOpUnary
tcg: Convert deposit to TCGOutOpDeposit
tcg/aarch64: Improve deposit
tcg: Merge INDEX_op_deposit_{i32,i64}
tcg: Convert extract2 to TCGOutOpExtract2
tcg: Merge INDEX_op_extract2_{i32,i64}
tcg: Expand fallback add2 with 32-bit operations
tcg: Expand fallback sub2 with 32-bit operations
tcg: Do not default add2/sub2_i32 for 32-bit hosts
tcg/mips: Drop support for add2/sub2
tcg/riscv: Drop support for add2/sub2
tcg: Move i into each for loop in liveness_pass_1
tcg: Sink def, nb_iargs, nb_oargs loads in liveness_pass_1
tcg: Add add/sub with carry opcodes and infrastructure
tcg: Add TCGOutOp structures for add/sub carry opcodes
tcg/optimize: Handle add/sub with carry opcodes
tcg/optimize: With two const operands, prefer 0 in arg1
tcg: Use add carry opcodes to expand add2
tcg: Use sub carry opcodes to expand sub2
tcg/i386: Honor carry_live in tcg_out_movi
tcg/i386: Implement add/sub carry opcodes
tcg/i386: Special case addci r, 0, 0
tcg: Add tcg_gen_addcio_{i32,i64,tl}
target/arm: Use tcg_gen_addcio_* for ADCS
target/hppa: Use tcg_gen_addcio_i64
target/microblaze: Use tcg_gen_addcio_i32
target/openrisc: Use tcg_gen_addcio_* for ADDC
target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF
target/s390x: Use tcg_gen_addcio_i64 for op_addc64
target/sh4: Use tcg_gen_addcio_i32 for addc
target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int
target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC
tcg/aarch64: Implement add/sub carry opcodes
tcg/arm: Implement add/sub carry opcodes
tcg/ppc: Implement add/sub carry opcodes
tcg/s390x: Honor carry_live in tcg_out_movi
tcg/s390x: Add TCG_CT_CONST_N32
tcg/s390x: Implement add/sub carry opcodes
tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE
tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc
tcg/sparc64: Implement add/sub carry opcodes
tcg/tci: Implement add/sub carry opcodes
tcg: Remove add2/sub2 opcodes
tcg: Formalize tcg_out_mb
tcg: Formalize tcg_out_br
tcg: Formalize tcg_out_goto_ptr
tcg: Convert ld to TCGOutOpLoad
tcg: Merge INDEX_op_ld*_{i32,i64}
tcg: Convert st to TCGOutOpStore
tcg: Merge INDEX_op_st*_{i32,i64}
tcg: Stash MemOp size in TCGOP_FLAGS
tcg: Remove INDEX_op_qemu_st8_*
tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}
tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}
tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}
tcg: Remove tcg_out_op
tcg/sparc64: Unexport use_vis3_instructions
tcg/sparc64: Implement CTPOP
include/tcg/tcg-op-common.h | 4 +
include/tcg/tcg-op.h | 2 +
include/tcg/tcg-opc.h | 212 ++--
include/tcg/tcg.h | 15 +-
tcg/aarch64/tcg-target-con-set.h | 5 +-
tcg/aarch64/tcg-target-has.h | 57 -
tcg/arm/tcg-target-con-set.h | 5 +-
tcg/arm/tcg-target-has.h | 27 -
tcg/i386/tcg-target-con-set.h | 4 +-
tcg/i386/tcg-target-con-str.h | 2 +-
tcg/i386/tcg-target-has.h | 57 -
tcg/loongarch64/tcg-target-con-set.h | 9 +-
tcg/loongarch64/tcg-target-con-str.h | 1 -
tcg/loongarch64/tcg-target-has.h | 60 --
tcg/mips/tcg-target-con-set.h | 15 +-
tcg/mips/tcg-target-con-str.h | 1 -
tcg/mips/tcg-target-has.h | 64 --
tcg/ppc/tcg-target-con-set.h | 12 +-
tcg/ppc/tcg-target-con-str.h | 1 +
tcg/ppc/tcg-target-has.h | 59 -
tcg/riscv/tcg-target-con-set.h | 7 +-
tcg/riscv/tcg-target-con-str.h | 2 -
tcg/riscv/tcg-target-has.h | 61 --
tcg/s390x/tcg-target-con-set.h | 7 +-
tcg/s390x/tcg-target-con-str.h | 1 +
tcg/s390x/tcg-target-has.h | 57 -
tcg/sparc64/tcg-target-con-set.h | 9 +-
tcg/sparc64/tcg-target-has.h | 65 --
tcg/tcg-has.h | 47 -
tcg/tcg-internal.h | 4 +-
tcg/tci/tcg-target-has.h | 59 -
target/arm/tcg/translate-a64.c | 10 +-
target/arm/tcg/translate-sve.c | 2 +-
target/arm/tcg/translate.c | 17 +-
target/hppa/translate.c | 17 +-
target/microblaze/translate.c | 10 +-
target/openrisc/translate.c | 3 +-
target/ppc/translate.c | 11 +-
target/s390x/tcg/translate.c | 6 +-
target/sh4/translate.c | 36 +-
target/sparc/translate.c | 3 +-
target/tricore/translate.c | 12 +-
tcg/optimize.c | 1080 +++++++++++--------
tcg/tcg-op-ldst.c | 74 +-
tcg/tcg-op.c | 1242 ++++++++++-----------
tcg/tcg.c | 1313 +++++++++++++++-------
tcg/tci.c | 766 +++++--------
docs/devel/tcg-ops.rst | 228 ++--
target/i386/tcg/emit.c.inc | 12 +-
tcg/aarch64/tcg-target.c.inc | 1626 ++++++++++++++++------------
tcg/arm/tcg-target.c.inc | 1556 ++++++++++++++++----------
tcg/i386/tcg-target.c.inc | 1850 ++++++++++++++++++-------------
tcg/loongarch64/tcg-target.c.inc | 1473 ++++++++++++++-----------
tcg/mips/tcg-target.c.inc | 1703 ++++++++++++++++-------------
tcg/ppc/tcg-target.c.inc | 1978 +++++++++++++++++++---------------
tcg/riscv/tcg-target.c.inc | 1375 ++++++++++++-----------
tcg/s390x/tcg-target.c.inc | 1945 ++++++++++++++++++---------------
tcg/sparc64/tcg-target.c.inc | 1337 +++++++++++++++--------
tcg/tci/tcg-target-opc.h.inc | 11 +
tcg/tci/tcg-target.c.inc | 1175 +++++++++++++-------
60 files changed, 12181 insertions(+), 9621 deletions(-)
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PULL v2 152/161] tcg: Convert st to TCGOutOpStore
2025-04-29 17:43 [PULL v2 000/161] tcg patch queue Richard Henderson
@ 2025-04-29 17:43 ` Richard Henderson
2025-04-29 17:43 ` [PULL v2 160/161] tcg/sparc64: Unexport use_vis3_instructions Richard Henderson
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2025-04-29 17:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Pierrick Bouvier
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 37 ++++++++++
tcg/aarch64/tcg-target.c.inc | 52 +++++++-------
tcg/arm/tcg-target.c.inc | 72 +++++++++----------
tcg/i386/tcg-target.c.inc | 114 ++++++++++++++-----------------
tcg/loongarch64/tcg-target.c.inc | 50 +++++++-------
tcg/mips/tcg-target.c.inc | 55 ++++++++-------
tcg/ppc/tcg-target.c.inc | 52 +++++++-------
tcg/riscv/tcg-target.c.inc | 52 +++++++-------
tcg/s390x/tcg-target.c.inc | 60 ++++++++--------
tcg/sparc64/tcg-target.c.inc | 53 +++++++-------
tcg/tci/tcg-target.c.inc | 56 ++++++++-------
11 files changed, 341 insertions(+), 312 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index a9d62d9e17..28791c6567 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1090,6 +1090,14 @@ typedef struct TCGOutOpSetcond2 {
TCGArg bl, bool const_bl, TCGArg bh, bool const_bh);
} TCGOutOpSetcond2;
+typedef struct TCGOutOpStore {
+ TCGOutOp base;
+ void (*out_r)(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, intptr_t offset);
+ void (*out_i)(TCGContext *s, TCGType type, tcg_target_long data,
+ TCGReg base, intptr_t offset);
+} TCGOutOpStore;
+
typedef struct TCGOutOpSubtract {
TCGOutOp base;
void (*out_rrr)(TCGContext *s, TCGType type,
@@ -1211,6 +1219,12 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_sextract, TCGOutOpExtract, outop_sextract),
OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl),
OUTOP(INDEX_op_shr, TCGOutOpBinary, outop_shr),
+ OUTOP(INDEX_op_st_i32, TCGOutOpStore, outop_st),
+ OUTOP(INDEX_op_st_i64, TCGOutOpStore, outop_st),
+ OUTOP(INDEX_op_st8_i32, TCGOutOpStore, outop_st8),
+ OUTOP(INDEX_op_st8_i64, TCGOutOpStore, outop_st8),
+ OUTOP(INDEX_op_st16_i32, TCGOutOpStore, outop_st16),
+ OUTOP(INDEX_op_st16_i64, TCGOutOpStore, outop_st16),
OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub),
OUTOP(INDEX_op_subbi, TCGOutOpAddSubCarry, outop_subbi),
OUTOP(INDEX_op_subbio, TCGOutOpAddSubCarry, outop_subbio),
@@ -1232,6 +1246,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_extrh_i64_i32, TCGOutOpUnary, outop_extrh_i64_i32),
OUTOP(INDEX_op_ld32u, TCGOutOpLoad, outop_ld32u),
OUTOP(INDEX_op_ld32s, TCGOutOpLoad, outop_ld32s),
+ OUTOP(INDEX_op_st32_i64, TCGOutOpStore, outop_st),
#endif
};
@@ -5779,6 +5794,28 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
break;
+ case INDEX_op_st32_i64:
+ /* Use tcg_op_st w/ I32. */
+ type = TCG_TYPE_I32;
+ /* fall through */
+ case INDEX_op_st_i32:
+ case INDEX_op_st_i64:
+ case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
+ {
+ const TCGOutOpStore *out =
+ container_of(all_outop[op->opc], TCGOutOpStore, base);
+
+ if (const_args[0]) {
+ out->out_i(s, type, new_args[0], new_args[1], new_args[2]);
+ } else {
+ out->out_r(s, type, new_args[0], new_args[1], new_args[2]);
+ }
+ }
+ break;
+
case INDEX_op_brcond:
{
const TCGOutOpBrcond *out = &outop_brcond;
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 903a95ad7e..39a44507d1 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2838,6 +2838,33 @@ static const TCGOutOpLoad outop_ld32s = {
.out = tgen_ld32s,
};
+static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, I3312_STRB, data, base, offset, 0);
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st8_r,
+};
+
+static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, I3312_STRH, data, base, offset, 1);
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st16_r,
+};
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tcg_out_st,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
@@ -2848,22 +2875,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
TCGArg a2 = args[2];
switch (opc) {
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- tcg_out_ldst(s, I3312_STRB, a0, a1, a2, 0);
- break;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- tcg_out_ldst(s, I3312_STRH, a0, a1, a2, 1);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- tcg_out_ldst(s, I3312_STRW, a0, a1, a2, 2);
- break;
- case INDEX_op_st_i64:
- tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3);
- break;
-
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
tcg_out_qemu_ld(s, a0, a1, a2, ext);
@@ -3331,15 +3342,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return C_O0_I2(rz, r);
-
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
return C_O1_I1(r, r);
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 2079dd3bdc..5b34f61ca1 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1084,26 +1084,6 @@ static void tcg_out_st32(TCGContext *s, ARMCond cond,
tcg_out_st32_12(s, cond, rd, rn, offset);
}
-static void tcg_out_st16(TCGContext *s, ARMCond cond,
- TCGReg rd, TCGReg rn, int32_t offset)
-{
- if (offset > 0xff || offset < -0xff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_st16_8(s, cond, rd, rn, offset);
-}
-
-static void tcg_out_st8(TCGContext *s, ARMCond cond,
- TCGReg rd, TCGReg rn, int32_t offset)
-{
- if (offset > 0xfff || offset < -0xfff) {
- tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
- tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP);
- } else
- tcg_out_st8_12(s, cond, rd, rn, offset);
-}
-
/*
* The _goto case is normally between TBs within the same code buffer, and
* with the code buffer limited to 16MB we wouldn't need the long case.
@@ -2548,21 +2528,48 @@ static const TCGOutOpLoad outop_ld16s = {
.out = tgen_ld16s,
};
+static void tgen_st8(TCGContext *s, TCGType type, TCGReg rd,
+ TCGReg rn, ptrdiff_t offset)
+{
+ if (offset > 0xfff || offset < -0xfff) {
+ tcg_out_movi32(s, COND_AL, TCG_REG_TMP, offset);
+ tcg_out_st8_r(s, COND_AL, rd, rn, TCG_REG_TMP);
+ } else {
+ tcg_out_st8_12(s, COND_AL, rd, rn, offset);
+ }
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tgen_st8,
+};
+
+static void tgen_st16(TCGContext *s, TCGType type, TCGReg rd,
+ TCGReg rn, ptrdiff_t offset)
+{
+ if (offset > 0xff || offset < -0xff) {
+ tcg_out_movi32(s, COND_AL, TCG_REG_TMP, offset);
+ tcg_out_st16_r(s, COND_AL, rd, rn, TCG_REG_TMP);
+ } else {
+ tcg_out_st16_8(s, COND_AL, rd, rn, offset);
+ }
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tgen_st16,
+};
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tcg_out_st,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
switch (opc) {
- case INDEX_op_st8_i32:
- tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_st16_i32:
- tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i32:
- tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
- break;
-
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
break;
@@ -2589,11 +2596,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- return C_O0_I2(r, r);
-
case INDEX_op_qemu_ld_i32:
return C_O1_I1(r, q);
case INDEX_op_qemu_ld_i64:
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index d16ddcb940..52285bcd54 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3489,55 +3489,69 @@ static const TCGOutOpLoad outop_ld32s = {
};
#endif
+static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, data, base, offset);
+}
+
+static void tgen_st8_i(TCGContext *s, TCGType type, tcg_target_long data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, base, offset);
+ tcg_out8(s, data);
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(qi, r),
+ .out_r = tgen_st8_r,
+ .out_i = tgen_st8_i,
+};
+
+static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, data, base, offset);
+}
+
+static void tgen_st16_i(TCGContext *s, TCGType type, tcg_target_long data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, base, offset);
+ tcg_out16(s, data);
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(ri, r),
+ .out_r = tgen_st16_r,
+ .out_i = tgen_st16_i,
+};
+
+static void tgen_st_i(TCGContext *s, TCGType type, tcg_target_long data,
+ TCGReg base, ptrdiff_t offset)
+{
+ bool ok = tcg_out_sti(s, type, data, base, offset);
+ tcg_debug_assert(ok);
+}
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(re, r),
+ .out_r = tcg_out_st,
+ .out_i = tgen_st_i,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0, a1, a2;
-#if TCG_TARGET_REG_BITS == 64
-# define OP_32_64(x) \
- case glue(glue(INDEX_op_, x), _i64): \
- case glue(glue(INDEX_op_, x), _i32)
-#else
-# define OP_32_64(x) \
- case glue(glue(INDEX_op_, x), _i32)
-#endif
-
/* Hoist the loads of the most common arguments. */
a0 = args[0];
a1 = args[1];
a2 = args[2];
switch (opc) {
- OP_32_64(st8):
- if (const_args[0]) {
- tcg_out_modrm_offset(s, OPC_MOVB_EvIz, 0, a1, a2);
- tcg_out8(s, a0);
- } else {
- tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R, a0, a1, a2);
- }
- break;
- OP_32_64(st16):
- if (const_args[0]) {
- tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_DATA16, 0, a1, a2);
- tcg_out16(s, a0);
- } else {
- tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16, a0, a1, a2);
- }
- break;
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_st32_i64:
-#endif
- case INDEX_op_st_i32:
- if (const_args[0]) {
- tcg_out_modrm_offset(s, OPC_MOVL_EvIz, 0, a1, a2);
- tcg_out32(s, a0);
- } else {
- tcg_out_st(s, TCG_TYPE_I32, a0, a1, a2);
- }
- break;
-
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32);
break;
@@ -3569,25 +3583,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128);
break;
-#if TCG_TARGET_REG_BITS == 64
- case INDEX_op_st_i64:
- if (const_args[0]) {
- tcg_out_modrm_offset(s, OPC_MOVL_EvIz | P_REXW, 0, a1, a2);
- tcg_out32(s, a0);
- } else {
- tcg_out_st(s, TCG_TYPE_I64, a0, a1, a2);
- }
- break;
-#endif
-
case INDEX_op_call: /* Always emitted via tcg_out_call. */
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
default:
g_assert_not_reached();
}
-
-#undef OP_32_64
}
static int const umin_insn[4] = {
@@ -4135,19 +4136,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- return C_O0_I2(qi, r);
-
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- return C_O0_I2(ri, r);
-
- case INDEX_op_st_i64:
- return C_O0_I2(re, r);
-
case INDEX_op_qemu_ld_i32:
return C_O1_I1(r, L);
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 66555b8982..73a1196d8b 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1983,6 +1983,33 @@ static const TCGOutOpLoad outop_ld32s = {
.out = tgen_ld32s,
};
+static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, OPC_ST_B, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st8_r,
+};
+
+static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, OPC_ST_H, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st16_r,
+};
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tcg_out_st,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
@@ -1993,22 +2020,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
TCGArg a3 = args[3];
switch (opc) {
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- tcg_out_ldst(s, OPC_ST_B, a0, a1, a2);
- break;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- tcg_out_ldst(s, OPC_ST_H, a0, a1, a2);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- tcg_out_ldst(s, OPC_ST_W, a0, a1, a2);
- break;
- case INDEX_op_st_i64:
- tcg_out_ldst(s, OPC_ST_D, a0, a1, a2);
- break;
-
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
break;
@@ -2530,13 +2541,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i32:
- case INDEX_op_st_i64:
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
return C_O0_I2(rz, r);
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 21ed11b78d..5e41729d88 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2342,12 +2342,38 @@ static const TCGOutOpLoad outop_ld32s = {
};
#endif
+static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, OPC_SB, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st8_r,
+};
+
+static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, OPC_SH, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st16_r,
+};
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tcg_out_st,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
- MIPSInsn i1;
TCGArg a0, a1, a2;
a0 = args[0];
@@ -2355,24 +2381,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
a2 = args[2];
switch (opc) {
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- i1 = OPC_SB;
- goto do_ldst;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- i1 = OPC_SH;
- goto do_ldst;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- i1 = OPC_SW;
- goto do_ldst;
- case INDEX_op_st_i64:
- i1 = OPC_SD;
- do_ldst:
- tcg_out_ldst(s, i1, a0, a1, a2);
- break;
-
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32);
break;
@@ -2407,15 +2415,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return C_O0_I2(rz, r);
-
case INDEX_op_qemu_ld_i32:
return C_O1_I1(r, r);
case INDEX_op_qemu_st_i32:
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 275c5a90a5..9cf24831df 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -3746,28 +3746,39 @@ static const TCGOutOpLoad outop_ld32s = {
};
#endif
+static void tgen_st8(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_mem_long(s, STB, STBX, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tgen_st8,
+};
+
+static void tgen_st16(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_mem_long(s, STH, STHX, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tgen_st16,
+};
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tcg_out_st,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
switch (opc) {
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
- break;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i64:
- tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
- break;
-
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
break;
@@ -4415,15 +4426,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return C_O0_I2(r, r);
-
case INDEX_op_qemu_ld_i32:
return C_O1_I1(r, r);
case INDEX_op_qemu_ld_i64:
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 5b987c930f..bcfdb6c545 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -2596,6 +2596,33 @@ static const TCGOutOpLoad outop_ld32s = {
.out = tgen_ld32s,
};
+static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, OPC_SB, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st8_r,
+};
+
+static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, OPC_SH, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st16_r,
+};
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tcg_out_st,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -2606,22 +2633,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
TCGArg a2 = args[2];
switch (opc) {
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- tcg_out_ldst(s, OPC_SB, a0, a1, a2);
- break;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- tcg_out_ldst(s, OPC_SH, a0, a1, a2);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- tcg_out_ldst(s, OPC_SW, a0, a1, a2);
- break;
- case INDEX_op_st_i64:
- tcg_out_ldst(s, OPC_SD, a0, a1, a2);
- break;
-
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
break;
@@ -2864,15 +2875,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return C_O0_I2(rz, r);
-
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
return C_O1_I1(r, r);
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index fe7665b21d..e266c19829 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -3100,29 +3100,39 @@ static const TCGOutOpLoad outop_ld32s = {
.out = tgen_ld32s,
};
-# define OP_32_64(x) \
- case glue(glue(INDEX_op_,x),_i32): \
- case glue(glue(INDEX_op_,x),_i64)
+static void tgen_st8(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_mem(s, RX_STC, RXY_STCY, data, base, TCG_REG_NONE, offset);
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tgen_st8,
+};
+
+static void tgen_st16(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_mem(s, RX_STH, RXY_STHY, data, base, TCG_REG_NONE, offset);
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tgen_st16,
+};
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tcg_out_st,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
switch (opc) {
- OP_32_64(st8):
- tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1],
- TCG_REG_NONE, args[2]);
- break;
-
- OP_32_64(st16):
- tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1],
- TCG_REG_NONE, args[2]);
- break;
-
- case INDEX_op_st_i32:
- tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
- break;
-
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32);
break;
@@ -3142,13 +3152,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false);
break;
- case INDEX_op_st32_i64:
- tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i64:
- tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
- break;
-
case INDEX_op_call: /* Always emitted via tcg_out_call. */
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
@@ -3597,15 +3600,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return C_O0_I2(r, r);
-
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
return C_O1_I1(r, r);
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 59a737dde4..a0efeee98c 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -2028,6 +2028,33 @@ static const TCGOutOpLoad outop_ld32s = {
.out = tgen_ld32s,
};
+static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, data, base, offset, STB);
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st8_r,
+};
+
+static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, data, base, offset, STH);
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tgen_st16_r,
+};
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(rz, r),
+ .out_r = tcg_out_st,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -2041,21 +2068,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
a2 = args[2];
switch (opc) {
-#define OP_32_64(x) \
- glue(glue(case INDEX_op_, x), _i32): \
- glue(glue(case INDEX_op_, x), _i64)
-
- OP_32_64(st8):
- tcg_out_ldst(s, a0, a1, a2, STB);
- break;
- OP_32_64(st16):
- tcg_out_ldst(s, a0, a1, a2, STH);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- tcg_out_ldst(s, a0, a1, a2, STW);
- break;
-
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
break;
@@ -2069,10 +2081,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
break;
- case INDEX_op_st_i64:
- tcg_out_ldst(s, a0, a1, a2, STX);
- break;
-
case INDEX_op_call: /* Always emitted via tcg_out_call. */
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
@@ -2089,13 +2097,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_qemu_ld_i64:
return C_O1_I1(r, r);
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
return C_O0_I2(rz, r);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index d549dc90f5..be9270a861 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -40,15 +40,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return C_O0_I2(r, r);
-
case INDEX_op_qemu_ld_i32:
return C_O1_I1(r, r);
case INDEX_op_qemu_ld_i64:
@@ -487,18 +478,6 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func,
tcg_out32(s, insn);
}
-#if TCG_TARGET_REG_BITS == 64
-# define CASE_32_64(x) \
- case glue(glue(INDEX_op_, x), _i64): \
- case glue(glue(INDEX_op_, x), _i32):
-# define CASE_64(x) \
- case glue(glue(INDEX_op_, x), _i64):
-#else
-# define CASE_32_64(x) \
- case glue(glue(INDEX_op_, x), _i32):
-# define CASE_64(x)
-#endif
-
static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg)
{
tcg_out_op_p(s, INDEX_op_exit_tb, (void *)arg);
@@ -1191,20 +1170,39 @@ static const TCGOutOpLoad outop_ld32s = {
};
#endif
+static void tgen_st8(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, INDEX_op_st8_i32, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st8 = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tgen_st8,
+};
+
+static void tgen_st16(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, ptrdiff_t offset)
+{
+ tcg_out_ldst(s, INDEX_op_st16_i32, data, base, offset);
+}
+
+static const TCGOutOpStore outop_st16 = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tgen_st16,
+};
+
+static const TCGOutOpStore outop_st = {
+ .base.static_constraint = C_O0_I2(r, r),
+ .out_r = tcg_out_st,
+};
+
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
switch (opc) {
- CASE_32_64(st8)
- CASE_32_64(st16)
- case INDEX_op_st_i32:
- CASE_64(st32)
- CASE_64(st)
- tcg_out_ldst(s, opc, args[0], args[1], args[2]);
- break;
-
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
if (TCG_TARGET_REG_BITS == 32) {
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PULL v2 160/161] tcg/sparc64: Unexport use_vis3_instructions
2025-04-29 17:43 [PULL v2 000/161] tcg patch queue Richard Henderson
2025-04-29 17:43 ` [PULL v2 152/161] tcg: Convert st to TCGOutOpStore Richard Henderson
@ 2025-04-29 17:43 ` Richard Henderson
2025-04-29 17:43 ` [PULL v2 161/161] tcg/sparc64: Implement CTPOP Richard Henderson
2025-04-30 19:04 ` [PULL v2 000/161] tcg patch queue Stefan Hajnoczi
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2025-04-29 17:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
This variable is no longer used outside tcg-target.c.inc.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc64/tcg-target-has.h | 6 ------
tcg/sparc64/tcg-target.c.inc | 6 ++++--
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h
index af6a949da3..b29fd177f6 100644
--- a/tcg/sparc64/tcg-target-has.h
+++ b/tcg/sparc64/tcg-target-has.h
@@ -7,12 +7,6 @@
#ifndef TCG_TARGET_HAS_H
#define TCG_TARGET_HAS_H
-#if defined(__VIS__) && __VIS__ >= 0x300
-#define use_vis3_instructions 1
-#else
-extern bool use_vis3_instructions;
-#endif
-
/* optional instructions */
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 83167aa29d..260dd461bd 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -274,8 +274,10 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
-#ifndef use_vis3_instructions
-bool use_vis3_instructions;
+#if defined(__VIS__) && __VIS__ >= 0x300
+#define use_vis3_instructions 1
+#else
+static bool use_vis3_instructions;
#endif
static bool check_fit_i64(int64_t val, unsigned int bits)
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PULL v2 161/161] tcg/sparc64: Implement CTPOP
2025-04-29 17:43 [PULL v2 000/161] tcg patch queue Richard Henderson
2025-04-29 17:43 ` [PULL v2 152/161] tcg: Convert st to TCGOutOpStore Richard Henderson
2025-04-29 17:43 ` [PULL v2 160/161] tcg/sparc64: Unexport use_vis3_instructions Richard Henderson
@ 2025-04-29 17:43 ` Richard Henderson
2025-04-30 19:04 ` [PULL v2 000/161] tcg patch queue Stefan Hajnoczi
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2025-04-29 17:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc64/tcg-target.c.inc | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 260dd461bd..9e004fb511 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -210,6 +210,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
+#define ARITH_POPC (INSN_OP(2) | INSN_OP3(0x2e))
#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11))
@@ -274,6 +275,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
+static bool use_popc_instructions;
#if defined(__VIS__) && __VIS__ >= 0x300
#define use_vis3_instructions 1
#else
@@ -1511,8 +1513,23 @@ static const TCGOutOpBinary outop_clz = {
.base.static_constraint = C_NotImplemented,
};
+static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
+{
+ tcg_out_arith(s, a0, TCG_REG_G0, a1, ARITH_POPC);
+}
+
+static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags)
+{
+ if (use_popc_instructions && type == TCG_TYPE_I64) {
+ return C_O1_I1(r, r);
+ }
+ return C_NotImplemented;
+}
+
static const TCGOutOpUnary outop_ctpop = {
- .base.static_constraint = C_NotImplemented,
+ .base.static_constraint = C_Dynamic,
+ .base.dynamic_constraint = cset_ctpop,
+ .out_rr = tgen_ctpop,
};
static const TCGOutOpBinary outop_ctz = {
@@ -2084,15 +2101,15 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
static void tcg_target_init(TCGContext *s)
{
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+
/*
* Only probe for the platform and capabilities if we haven't already
* determined maximum values at compile time.
*/
+ use_popc_instructions = (hwcap & HWCAP_SPARC_POPC) != 0;
#ifndef use_vis3_instructions
- {
- unsigned long hwcap = qemu_getauxval(AT_HWCAP);
- use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0;
- }
+ use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0;
#endif
tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PULL v2 000/161] tcg patch queue
2025-04-29 17:43 [PULL v2 000/161] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2025-04-29 17:43 ` [PULL v2 161/161] tcg/sparc64: Implement CTPOP Richard Henderson
@ 2025-04-30 19:04 ` Stefan Hajnoczi
3 siblings, 0 replies; 5+ messages in thread
From: Stefan Hajnoczi @ 2025-04-30 19:04 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-04-30 19:05 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2025-04-29 17:43 [PULL v2 000/161] tcg patch queue Richard Henderson
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2025-04-29 17:43 ` [PULL v2 160/161] tcg/sparc64: Unexport use_vis3_instructions Richard Henderson
2025-04-29 17:43 ` [PULL v2 161/161] tcg/sparc64: Implement CTPOP Richard Henderson
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