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From: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
To: qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, richard.henderson@linaro.org,
	eduardo@habkost.net, peterx@redhat.com, david@redhat.com,
	philmd@linaro.org, mst@redhat.com, marcel.apfelbaum@gmail.com,
	alex.williamson@redhat.com, vasant.hegde@amd.com,
	suravee.suthikulpanit@amd.com, santosh.shukla@amd.com,
	sarunkod@amd.com, Wei.Huang2@amd.com,
	clement.mathieu--drif@eviden.com, ethan.milon@eviden.com,
	joao.m.martins@oracle.com, boris.ostrovsky@oracle.com,
	alejandro.j.jimenez@oracle.com
Subject: [PATCH v2 04/20] amd_iommu: Helper to decode size of page invalidation command
Date: Fri,  2 May 2025 02:15:49 +0000	[thread overview]
Message-ID: <20250502021605.1795985-5-alejandro.j.jimenez@oracle.com> (raw)
In-Reply-To: <20250502021605.1795985-1-alejandro.j.jimenez@oracle.com>

The size of the region to invalidate depends on the S bit and address
encoded in the command. Add a helper to extract this information, which
will be used to sync shadow page tables in upcoming changes.

Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
---
 hw/i386/amd_iommu.c | 34 ++++++++++++++++++++++++++++++++++
 hw/i386/amd_iommu.h |  4 ++++
 2 files changed, 38 insertions(+)

diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 9e500121f6e8..dff6f04c8651 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -545,6 +545,40 @@ static gboolean amdvi_iotlb_remove_by_domid(gpointer key, gpointer value,
     return entry->domid == domid;
 }
 
+/*
+ * Helper to decode the size of the range to invalidate encoded in the
+ * INVALIDATE_IOMMU_PAGES Command format.
+ * The size of the region to invalidate depends on the S bit and address.
+ * S bit value:
+ * 0 :  Invalidation size is 4 Kbytes.
+ * 1 :  Invalidation size is determined by first zero bit in the address
+ *      starting from Address[12].
+ *
+ * In the AMD IOMMU Linux driver, an invalidation command with address
+ * ((1 << 63) - 1) is sent when intending to clear the entire cache.
+ * However, Table 14: Example Page Size Encodings shows that an address of
+ * ((1ULL << 51) - 1) encodes the entire cache, so effectively any address with
+ * first zero at bit 51 or larger is a request to invalidate the entire address
+ * space.
+ */
+static uint64_t __attribute__((unused))
+amdvi_decode_invalidation_size(hwaddr addr, uint16_t flags)
+{
+    uint64_t size = AMDVI_PAGE_SIZE;
+    uint8_t fzbit = 0;
+
+    if (flags & AMDVI_CMD_INVAL_IOMMU_PAGES_S) {
+        fzbit = cto64(addr | 0xFFF);
+
+        if (fzbit >= 51) {
+            size = AMDVI_INV_ALL_PAGES;
+        } else {
+            size = 1ULL << (fzbit + 1);
+        }
+    }
+    return size;
+}
+
 /* we don't have devid - we can't remove pages by address */
 static void amdvi_inval_pages(AMDVIState *s, uint64_t *cmd)
 {
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index 28125130c6fc..6f35b0595054 100644
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -123,6 +123,10 @@
 #define AMDVI_CMD_COMPLETE_PPR_REQUEST    0x07
 #define AMDVI_CMD_INVAL_AMDVI_ALL         0x08
 
+
+#define AMDVI_CMD_INVAL_IOMMU_PAGES_S   (1ULL << 0)
+#define AMDVI_INV_ALL_PAGES             (1ULL << 52)
+
 #define AMDVI_DEVTAB_ENTRY_SIZE           32
 
 /* Device table entry bits 0:63 */
-- 
2.43.5



  parent reply	other threads:[~2025-05-02  2:21 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-02  2:15 [PATCH v2 00/20] AMD vIOMMU: DMA remapping support for VFIO devices Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 01/20] memory: Adjust event ranges to fit within notifier boundaries Alejandro Jimenez
2025-05-11 18:31   ` Michael S. Tsirkin
2025-05-12  8:02   ` David Hildenbrand
2025-05-12 17:29     ` Peter Xu
2025-06-12  6:54   ` Vasant Hegde
2025-06-12 21:49     ` Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 02/20] amd_iommu: Document '-device amd-iommu' common options Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 03/20] amd_iommu: Reorder device and page table helpers Alejandro Jimenez
2025-05-02  2:15 ` Alejandro Jimenez [this message]
2025-05-02  2:15 ` [PATCH v2 05/20] amd_iommu: Add helper function to extract the DTE Alejandro Jimenez
2025-05-12  6:45   ` Sairaj Kodilkar
2025-05-14 20:23     ` Alejandro Jimenez
2025-05-20 10:18   ` Ethan MILON
2025-05-21 14:49     ` Alejandro Jimenez
2025-06-12  8:31       ` Ethan MILON
2025-05-02  2:15 ` [PATCH v2 06/20] amd_iommu: Return an error when unable to read PTE from guest memory Alejandro Jimenez
2025-06-12 10:37   ` Vasant Hegde
2025-06-13 17:44     ` Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 07/20] amd_iommu: Add helpers to walk AMD v1 Page Table format Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 08/20] amd_iommu: Add a page walker to sync shadow page tables on invalidation Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 09/20] amd_iommu: Add basic structure to support IOMMU notifier updates Alejandro Jimenez
2025-05-12  6:52   ` Sairaj Kodilkar
2025-06-23 10:53   ` Sairaj Kodilkar
2025-05-02  2:15 ` [PATCH v2 10/20] amd_iommu: Sync shadow page tables on page invalidation Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 11/20] amd_iommu: Use iova_tree records to determine large page size on UNMAP Alejandro Jimenez
2025-06-11  8:29   ` Sairaj Kodilkar
2025-06-13 21:50     ` Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 12/20] amd_iommu: Unmap all address spaces under the AMD IOMMU on reset Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 13/20] amd_iommu: Add replay callback Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 14/20] amd_iommu: Invalidate address translations on INVALIDATE_IOMMU_ALL Alejandro Jimenez
2025-05-02  2:16 ` [PATCH v2 15/20] amd_iommu: Toggle memory regions based on address translation mode Alejandro Jimenez
2025-05-12  6:52   ` Sairaj Kodilkar
2025-05-02  2:16 ` [PATCH v2 16/20] amd_iommu: Set all address spaces to default translation mode on reset Alejandro Jimenez
2025-05-29  6:16   ` Sairaj Kodilkar
2025-05-30 21:30     ` Alejandro Jimenez
2025-06-13  8:46       ` Sairaj Kodilkar
2025-06-23 22:08         ` Alejandro Jimenez
2025-05-02  2:16 ` [PATCH v2 17/20] amd_iommu: Add dma-remap property to AMD vIOMMU device Alejandro Jimenez
2025-05-02  2:16 ` [PATCH v2 18/20] amd_iommu: Toggle address translation mode on devtab entry invalidation Alejandro Jimenez
2025-06-12  8:27   ` Ethan MILON
2025-06-12 11:23     ` Sairaj Kodilkar
2025-05-02  2:16 ` [PATCH v2 19/20] amd_iommu: Do not assume passthrough translation when DTE[TV]=0 Alejandro Jimenez
2025-05-12  7:00   ` Sairaj Kodilkar
2025-05-14 21:49     ` Alejandro Jimenez
2025-05-16  8:14       ` Sairaj Kodilkar
2025-05-02  2:16 ` [PATCH v2 20/20] amd_iommu: Refactor amdvi_page_walk() to use common code for page walk Alejandro Jimenez
2025-05-11 18:34 ` [PATCH v2 00/20] AMD vIOMMU: DMA remapping support for VFIO devices Michael S. Tsirkin
2025-05-16  8:07 ` Sairaj Kodilkar
2025-05-21  2:35   ` Alejandro Jimenez
2025-05-21  6:21     ` Sairaj Kodilkar
2025-05-30 11:41 ` Michael S. Tsirkin
2025-05-30 14:39   ` Alejandro Jimenez
2025-06-02  4:49     ` Sairaj Kodilkar

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