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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30aae500d66sm1489788a91.7.2025.05.07.02.19.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 May 2025 02:19:09 -0700 (PDT) From: Tim Lee To: farosas@suse.de, lvivier@redhat.com, pbonzini@redhat.com, wuhaotsh@google.com, kfting@nuvoton.com, chli30@nuvoton.com Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Tim Lee Subject: [v2] tests/qtest: Add qtest for NPCM8XX PSPI module Date: Wed, 7 May 2025 17:18:59 +0800 Message-Id: <20250507091859.2507455-1-timlee660101@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=timlee660101@gmail.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org - Created qtest to check initialization of registers in PSPI Module - Implemented test into Build File Tested: ./build/tests/qtest/npcm8xx-pspi_test Signed-off-by: Tim Lee --- Changes since v1: - MAINTAINERS file not need to change - Add comment for copyright/license information - Correct CTL registers to use 16 bits - Remove printf() in test cases tests/qtest/meson.build | 3 + tests/qtest/npcm8xx_pspi-test.c | 118 ++++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+) create mode 100644 tests/qtest/npcm8xx_pspi-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 3136d15e0f..88672a8b00 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -210,6 +210,8 @@ qtests_npcm7xx = \ 'npcm7xx_watchdog_timer-test', 'npcm_gmac-test'] + \ (slirp.found() ? ['npcm7xx_emc-test'] : []) +qtests_npcm8xx = \ + ['npcm8xx_pspi-test'] qtests_aspeed = \ ['aspeed_hace-test', 'aspeed_smc-test', @@ -257,6 +259,7 @@ qtests_aarch64 = \ (config_all_accel.has_key('CONFIG_TCG') and \ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \ + (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', diff --git a/tests/qtest/npcm8xx_pspi-test.c b/tests/qtest/npcm8xx_pspi-test.c new file mode 100644 index 0000000000..13b8a8229c --- /dev/null +++ b/tests/qtest/npcm8xx_pspi-test.c @@ -0,0 +1,118 @@ +/* + * QTests for the Nuvoton NPCM8XX PSPI Controller + * + * Copyright (c) 2025 Nuvoton Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "qemu/module.h" + +/* Register offsets */ +#define DATA_OFFSET 0x00 +#define CTL_SPIEN 0x01 +#define CTL_OFFSET 0x02 +#define CTL_MOD 0x04 + +typedef struct PSPI { + uint64_t base_addr; +} PSPI; + +PSPI pspi_defs = { + .base_addr = 0xf0201000 +}; + +static uint16_t pspi_read_data(QTestState *qts, const PSPI *pspi) +{ + return qtest_readw(qts, pspi->base_addr + DATA_OFFSET); +} + +static void pspi_write_data(QTestState *qts, const PSPI *pspi, uint16_t value) +{ + qtest_writew(qts, pspi->base_addr + DATA_OFFSET, value); +} + +static uint16_t pspi_read_ctl(QTestState *qts, const PSPI *pspi) +{ + return qtest_readw(qts, pspi->base_addr + CTL_OFFSET); +} + +static void pspi_write_ctl(QTestState *qts, const PSPI *pspi, uint16_t value) +{ + qtest_writew(qts, pspi->base_addr + CTL_OFFSET, value); +} + +/* Check PSPI can be reset to default value */ +static void test_init(gconstpointer pspi_p) +{ + const PSPI *pspi = pspi_p; + + QTestState *qts = qtest_init("-machine npcm845-evb"); + + /* Write CTL_SPIEN value to control register for enable PSPI module */ + pspi_write_ctl(qts, pspi, CTL_SPIEN); + g_assert_cmphex(pspi_read_ctl(qts, pspi), ==, CTL_SPIEN); + + qtest_quit(qts); +} + +/* Check PSPI can be r/w data register */ +static void test_data(gconstpointer pspi_p) +{ + const PSPI *pspi = pspi_p; + uint16_t test = 0x1234; + uint16_t output; + + QTestState *qts = qtest_init("-machine npcm845-evb"); + + /* Enable 16-bit data interface mode */ + pspi_write_ctl(qts, pspi, CTL_MOD); + g_assert_cmphex(pspi_read_ctl(qts, pspi), ==, CTL_MOD); + + /* Write to data register */ + pspi_write_data(qts, pspi, test); + + /* Read from data register */ + output = pspi_read_data(qts, pspi); + g_assert_cmphex(output, ==, test); + + qtest_quit(qts); +} + +/* Check PSPI can be r/w control register */ +static void test_ctl(gconstpointer pspi_p) +{ + const PSPI *pspi = pspi_p; + uint8_t control = CTL_MOD; + + QTestState *qts = qtest_init("-machine npcm845-evb"); + + /* Write CTL_MOD value to control register for 16-bit interface mode */ + qtest_memwrite(qts, pspi->base_addr + CTL_OFFSET, + &control, sizeof(control)); + g_assert_cmphex(pspi_read_ctl(qts, pspi), ==, control); + + qtest_quit(qts); +} + +static void pspi_add_test(const char *name, const PSPI* wd, + GTestDataFunc fn) +{ + g_autofree char *full_name = g_strdup_printf("npcm8xx_pspi/%s", name); + qtest_add_data_func(full_name, wd, fn); +} + +#define add_test(name, td) pspi_add_test(#name, td, test_##name) + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + add_test(init, &pspi_defs); + add_test(ctl, &pspi_defs); + add_test(data, &pspi_defs); + return g_test_run(); +} -- 2.34.1