[PULL 00/32] target-arm queue

[PULL 00/32] target-arm queue

[Peter Maydell]

Now I'm back from holiday, here's a target-arm pullreq :-)

thanks
-- PMM

The following changes since commit a9e0c9c0f14e19d23443ac24c8080b4708d2eab8:

  Merge tag 'pull-9p-20250505' of https://github.com/cschoenebeck/qemu into staging (2025-05-05 11:26:59 -0400)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250506

for you to fetch changes up to 607e1208b53ac713a76d158f4abc4cd2e8870051:

  hw/arm/virt: Remove deprecated virt-4.0 machine (2025-05-06 15:02:35 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC
 * arm/hvf: fix crashes when using gdbstub
 * target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug
 * hw/arm/virt: Remove deprecated old versions of 'virt' machine
 * tests/functional: Add test for imx8mp-evk board with USDHC coverage
 * hw/arm: Attach PSPI module to NPCM8XX SoC
 * target/arm: Don't assert() for ISB/SB inside IT block
 * docs: Don't define duplicate label in qemu-block-drivers.rst.inc
 * target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET
 * hw/pci-host/designware: Fix viewport configuration
 * hw/gpio/imx_gpio: Fix interpretation of GDIR polarity

----------------------------------------------------------------
Bernhard Beschow (4):
      tests/functional: Add test for imx8mp-evk board with USDHC coverage
      hw/pci-host/designware: Remove unused include
      hw/pci-host/designware: Fix viewport configuration
      hw/gpio/imx_gpio: Fix interpretation of GDIR polarity

Mads Ynddal (2):
      hvf: avoid repeatedly setting trap debug for each cpu
      hvf: only update sysreg from owning thread

Peter Maydell (3):
      target/arm: Don't assert() for ISB/SB inside IT block
      docs: Don't define duplicate label in qemu-block-drivers.rst.inc
      target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET

Philippe Mathieu-Daudé (17):
      hw/arm/virt: Remove deprecated virt-2.6 machine
      hw/arm/virt: Remove VirtMachineClass::no_pmu field
      hw/arm/virt: Remove VirtMachineClass::disallow_affinity_adjustment
      hw/arm/virt: Remove deprecated virt-2.7 machine
      hw/arm/virt: Remove VirtMachineClass::no_its field
      hw/arm/virt: Remove deprecated virt-2.8 machine
      hw/arm/virt: Remove VirtMachineClass::claim_edge_triggered_timers field
      hw/arm/virt: Remove deprecated virt-2.9 machine
      hw/arm/virt: Remove deprecated virt-2.10 machine
      hw/arm/virt: Remove deprecated virt-2.11 machine
      hw/arm/virt: Remove VirtMachineClass::smbios_old_sys_ver field
      hw/arm/virt: Remove deprecated virt-2.12 machine
      hw/arm/virt: Remove VirtMachineClass::no_highmem_ecam field
      hw/arm/virt: Update comment about Multiprocessor Affinity Register
      hw/arm/virt: Remove deprecated virt-3.0 machine
      hw/arm/virt: Remove deprecated virt-3.1 machine
      hw/arm/virt: Remove deprecated virt-4.0 machine

Pierrick Bouvier (4):
      target/arm/ptw: extract arm_mmu_idx_to_security_space
      target/arm/ptw: get current security_space for current mmu_idx
      target/arm/ptw: extract arm_cpu_get_phys_page
      target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug

Tim Lee (2):
      hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC
      hw/arm: Attach PSPI module to NPCM8XX SoC

 MAINTAINERS                                 |   1 +
 docs/devel/codebase.rst                     |   2 +-
 docs/system/qemu-block-drivers.rst.inc      |   2 -
 include/hw/arm/npcm8xx.h                    |   2 +
 include/hw/arm/virt.h                       |   6 --
 target/arm/kvm_arm.h                        |   7 +-
 accel/hvf/hvf-all.c                         |   7 +-
 hw/arm/npcm8xx.c                            |  11 +-
 hw/arm/npcm8xx_boards.c                     |   2 +-
 hw/arm/virt-acpi-build.c                    |  10 +-
 hw/arm/virt.c                               | 153 ++++------------------------
 hw/gpio/imx_gpio.c                          |   2 +-
 hw/pci-host/designware.c                    |   5 +-
 target/arm/arm-qmp-cmds.c                   |   2 +-
 target/arm/hvf/hvf.c                        |  27 ++---
 target/arm/kvm.c                            |  55 ++--------
 target/arm/ptw.c                            |  71 +++++++++----
 target/arm/tcg/translate.c                  |   3 +-
 tests/functional/meson.build                |   2 +
 tests/functional/test_aarch64_imx8mp_evk.py |  67 ++++++++++++
 20 files changed, 188 insertions(+), 249 deletions(-)
 create mode 100755 tests/functional/test_aarch64_imx8mp_evk.py

[PULL 01/32] hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC

[Peter Maydell]

From: Tim Lee <timlee660101@gmail.com>

NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
Correct the `valid_cpu_types` setting to match the NPCM8XX SoC.

Cc: qemu-stable@nongnu.org
Fixes: 7e70eb3cad7c83 ("hw/arm: Add NPCM845 Evaluation board")
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Message-id: 20250428022934.3081139-1-timlee660101@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm8xx_boards.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index 9d9f6d0c9a6..3bf3e1f8f16 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -213,7 +213,7 @@ static void npcm8xx_machine_class_init(ObjectClass *oc, const void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     static const char * const valid_cpu_types[] = {
-        ARM_CPU_TYPE_NAME("cortex-a9"),
+        ARM_CPU_TYPE_NAME("cortex-a35"),
         NULL
     };
 
-- 
2.43.0

[PULL 02/32] hvf: avoid repeatedly setting trap debug for each cpu

[Peter Maydell]

From: Mads Ynddal <m.ynddal@samsung.com>

hvf_arch_set_traps is already called from a context of a specific
CPUState, so we don't need to do a nested CPU_FOREACH.

It also results in an error from hv_vcpu_set_sys_reg, as it may only be
called from the thread owning the vCPU.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2895
Tested-by: Daniel Gomez <da.gomez@samsung.com>
Signed-off-by: Mads Ynddal <m.ynddal@samsung.com>
Reported-by: Daniel Gomez <da.gomez@samsung.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250402135229.28143-2-mads@ynddal.dk
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/hvf/hvf.c | 27 +++++++++++----------------
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 34ca36fab55..42258cc2d88 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -2278,28 +2278,23 @@ static inline bool hvf_arm_hw_debug_active(CPUState *cpu)
     return ((cur_hw_wps > 0) || (cur_hw_bps > 0));
 }
 
-static void hvf_arch_set_traps(void)
+static void hvf_arch_set_traps(CPUState *cpu)
 {
-    CPUState *cpu;
     bool should_enable_traps = false;
     hv_return_t r = HV_SUCCESS;
 
     /* Check whether guest debugging is enabled for at least one vCPU; if it
      * is, enable exiting the guest on all vCPUs */
-    CPU_FOREACH(cpu) {
-        should_enable_traps |= cpu->accel->guest_debug_enabled;
-    }
-    CPU_FOREACH(cpu) {
-        /* Set whether debug exceptions exit the guest */
-        r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd,
-                                              should_enable_traps);
-        assert_hvf_ok(r);
+    should_enable_traps |= cpu->accel->guest_debug_enabled;
+    /* Set whether debug exceptions exit the guest */
+    r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd,
+                                            should_enable_traps);
+    assert_hvf_ok(r);
 
-        /* Set whether accesses to debug registers exit the guest */
-        r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd,
-                                                should_enable_traps);
-        assert_hvf_ok(r);
-    }
+    /* Set whether accesses to debug registers exit the guest */
+    r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd,
+                                            should_enable_traps);
+    assert_hvf_ok(r);
 }
 
 void hvf_arch_update_guest_debug(CPUState *cpu)
@@ -2340,7 +2335,7 @@ void hvf_arch_update_guest_debug(CPUState *cpu)
             deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0);
     }
 
-    hvf_arch_set_traps();
+    hvf_arch_set_traps(cpu);
 }
 
 bool hvf_arch_supports_guest_debug(void)
-- 
2.43.0

[PULL 03/32] hvf: only update sysreg from owning thread

[Peter Maydell]

From: Mads Ynddal <m.ynddal@samsung.com>

hv_vcpu_set_sys_reg should only be called from the owning thread of the
vCPU, so to avoid crashes, the call to hvf_update_guest_debug is
dispatched to the individual threads.

Tested-by: Daniel Gomez <da.gomez@samsung.com>
Signed-off-by: Mads Ynddal <m.ynddal@samsung.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250402135229.28143-3-mads@ynddal.dk
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 accel/hvf/hvf-all.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c
index d404e01adef..3fc65d6b231 100644
--- a/accel/hvf/hvf-all.c
+++ b/accel/hvf/hvf-all.c
@@ -58,8 +58,13 @@ int hvf_sw_breakpoints_active(CPUState *cpu)
     return !QTAILQ_EMPTY(&hvf_state->hvf_sw_breakpoints);
 }
 
-int hvf_update_guest_debug(CPUState *cpu)
+static void do_hvf_update_guest_debug(CPUState *cpu, run_on_cpu_data arg)
 {
     hvf_arch_update_guest_debug(cpu);
+}
+
+int hvf_update_guest_debug(CPUState *cpu)
+{
+    run_on_cpu(cpu, do_hvf_update_guest_debug, RUN_ON_CPU_NULL);
     return 0;
 }
-- 
2.43.0

[PULL 04/32] target/arm/ptw: extract arm_mmu_idx_to_security_space

[Peter Maydell]

From: Pierrick Bouvier <pierrick.bouvier@linaro.org>

We'll reuse this function later.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20250414153027.1486719-2-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index e0e82ae507f..bdb4de7c047 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3551,13 +3551,9 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address,
                                memop, result, fi);
 }
 
-bool get_phys_addr(CPUARMState *env, vaddr address,
-                   MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx,
-                   GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+static ARMSecuritySpace
+arm_mmu_idx_to_security_space(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
-    S1Translate ptw = {
-        .in_mmu_idx = mmu_idx,
-    };
     ARMSecuritySpace ss;
 
     switch (mmu_idx) {
@@ -3618,7 +3614,18 @@ bool get_phys_addr(CPUARMState *env, vaddr address,
         g_assert_not_reached();
     }
 
-    ptw.in_space = ss;
+    return ss;
+}
+
+bool get_phys_addr(CPUARMState *env, vaddr address,
+                   MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx,
+                   GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
+{
+    S1Translate ptw = {
+        .in_mmu_idx = mmu_idx,
+        .in_space = arm_mmu_idx_to_security_space(env, mmu_idx),
+    };
+
     return get_phys_addr_gpc(env, &ptw, address, access_type,
                              memop, result, fi);
 }
-- 
2.43.0

[PULL 05/32] target/arm/ptw: get current security_space for current mmu_idx

[Peter Maydell]

From: Pierrick Bouvier <pierrick.bouvier@linaro.org>

It should be equivalent to previous code.
Allow to call common function to get a page address later.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20250414153027.1486719-3-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index bdb4de7c047..0ae9c5a3f49 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3636,7 +3636,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
     ARMMMUIdx mmu_idx = arm_mmu_idx(env);
-    ARMSecuritySpace ss = arm_security_space(env);
+    ARMSecuritySpace ss = arm_mmu_idx_to_security_space(env, mmu_idx);
     S1Translate ptw = {
         .in_mmu_idx = mmu_idx,
         .in_space = ss,
-- 
2.43.0

[PULL 06/32] target/arm/ptw: extract arm_cpu_get_phys_page

[Peter Maydell]

From: Pierrick Bouvier <pierrick.bouvier@linaro.org>

Allow to call that function easily several times in next commit.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20250414153027.1486719-4-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 0ae9c5a3f49..3e00e4a8bb4 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3630,23 +3630,17 @@ bool get_phys_addr(CPUARMState *env, vaddr address,
                              memop, result, fi);
 }
 
-hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
-                                         MemTxAttrs *attrs)
+static hwaddr arm_cpu_get_phys_page(CPUARMState *env, vaddr addr,
+                                    MemTxAttrs *attrs, ARMMMUIdx mmu_idx)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
-    ARMMMUIdx mmu_idx = arm_mmu_idx(env);
-    ARMSecuritySpace ss = arm_mmu_idx_to_security_space(env, mmu_idx);
     S1Translate ptw = {
         .in_mmu_idx = mmu_idx,
-        .in_space = ss,
+        .in_space = arm_mmu_idx_to_security_space(env, mmu_idx),
         .in_debug = true,
     };
     GetPhysAddrResult res = {};
     ARMMMUFaultInfo fi = {};
-    bool ret;
-
-    ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, 0, &res, &fi);
+    bool ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, 0, &res, &fi);
     *attrs = res.f.attrs;
 
     if (ret) {
@@ -3654,3 +3648,13 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
     }
     return res.f.phys_addr;
 }
+
+hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
+                                         MemTxAttrs *attrs)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    ARMMMUIdx mmu_idx = arm_mmu_idx(env);
+
+    return arm_cpu_get_phys_page(env, addr, attrs, mmu_idx);
+}
-- 
2.43.0

[PULL 07/32] target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug

[Peter Maydell]

From: Pierrick Bouvier <pierrick.bouvier@linaro.org>

It was reported that QEMU monitor command gva2gpa was reporting unmapped
memory for a valid access (qemu-system-aarch64), during a copy from
kernel to user space (__arch_copy_to_user symbol in Linux) [1].
This was affecting cpu_memory_rw_debug also, which
is used in numerous places in our codebase. After investigating, the
problem was specific to arm_cpu_get_phys_page_attrs_debug.

When performing user access from a privileged space, we need to do a
second lookup for user mmu idx, following what get_a64_user_mem_index is
doing at translation time.

[1] https://lists.nongnu.org/archive/html/qemu-discuss/2025-04/msg00013.html

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20250414153027.1486719-5-pierrick.bouvier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 3e00e4a8bb4..d0a53d0987f 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3656,5 +3656,25 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
     CPUARMState *env = &cpu->env;
     ARMMMUIdx mmu_idx = arm_mmu_idx(env);
 
-    return arm_cpu_get_phys_page(env, addr, attrs, mmu_idx);
+    hwaddr res = arm_cpu_get_phys_page(env, addr, attrs, mmu_idx);
+
+    if (res != -1) {
+        return res;
+    }
+
+    /*
+     * Memory may be accessible for an "unprivileged load/store" variant.
+     * In this case, get_a64_user_mem_index function generates an op using an
+     * unprivileged mmu idx, so we need to try with it.
+     */
+    switch (mmu_idx) {
+    case ARMMMUIdx_E10_1:
+    case ARMMMUIdx_E10_1_PAN:
+        return arm_cpu_get_phys_page(env, addr, attrs, ARMMMUIdx_E10_0);
+    case ARMMMUIdx_E20_2:
+    case ARMMMUIdx_E20_2_PAN:
+        return arm_cpu_get_phys_page(env, addr, attrs, ARMMMUIdx_E20_0);
+    default:
+        return -1;
+    }
 }
-- 
2.43.0

[PULL 08/32] hw/arm/virt: Remove deprecated virt-2.6 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 177f3dd22c1..17a88aa9b25 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3667,15 +3667,3 @@ static void virt_machine_2_7_options(MachineClass *mc)
     mc->minimum_page_bits = 0;
 }
 DEFINE_VIRT_MACHINE(2, 7)
-
-static void virt_machine_2_6_options(MachineClass *mc)
-{
-    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
-
-    virt_machine_2_7_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
-    vmc->disallow_affinity_adjustment = true;
-    /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
-    vmc->no_pmu = true;
-}
-DEFINE_VIRT_MACHINE(2, 6)
-- 
2.43.0

[PULL 09/32] hw/arm/virt: Remove VirtMachineClass::no_pmu field

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The VirtMachineClass::no_pmu field was only used by
virt-2.6 machine, which got removed. Remove it and
simplify machvirt_init().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h | 1 -
 hw/arm/virt.c         | 4 ----
 2 files changed, 5 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index c8e94e6aedc..27c5bb585cb 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -120,7 +120,6 @@ struct VirtMachineClass {
     bool disallow_affinity_adjustment;
     bool no_its;
     bool no_tcg_its;
-    bool no_pmu;
     bool claim_edge_triggered_timers;
     bool smbios_old_sys_ver;
     bool no_highmem_compact;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 17a88aa9b25..e82b8a45664 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2273,10 +2273,6 @@ static void machvirt_init(MachineState *machine)
             object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
         }
 
-        if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
-            object_property_set_bool(cpuobj, "pmu", false, NULL);
-        }
-
         if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
             object_property_set_bool(cpuobj, "lpa2", false, NULL);
         }
-- 
2.43.0

[PULL 10/32] hw/arm/virt: Remove VirtMachineClass::disallow_affinity_adjustment

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The VirtMachineClass::disallow_affinity_adjustment
field was only used by virt-2.6 machine, which got
removed. Remove it and simplify virt_cpu_mp_affinity().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
[PMM: Remove now-unused variable]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h |  1 -
 hw/arm/virt.c         | 31 +++++++++++++++----------------
 2 files changed, 15 insertions(+), 17 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 27c5bb585cb..5d3b25509ff 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -117,7 +117,6 @@ typedef enum VirtGICType {
 
 struct VirtMachineClass {
     MachineClass parent;
-    bool disallow_affinity_adjustment;
     bool no_its;
     bool no_tcg_its;
     bool claim_edge_triggered_timers;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e82b8a45664..9d82cf78b0e 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1770,24 +1770,23 @@ void virt_machine_done(Notifier *notifier, void *data)
 
 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
 {
-    uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
-    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
+    uint8_t clustersz;
 
-    if (!vmc->disallow_affinity_adjustment) {
-        /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
-         * GIC's target-list limitations. 32-bit KVM hosts currently
-         * always create clusters of 4 CPUs, but that is expected to
-         * change when they gain support for gicv3. When KVM is enabled
-         * it will override the changes we make here, therefore our
-         * purposes are to make TCG consistent (with 64-bit KVM hosts)
-         * and to improve SGI efficiency.
-         */
-        if (vms->gic_version == VIRT_GIC_VERSION_2) {
-            clustersz = GIC_TARGETLIST_BITS;
-        } else {
-            clustersz = GICV3_TARGETLIST_BITS;
-        }
+    /*
+     * Adjust MPIDR like 64-bit KVM hosts, which incorporate the
+     * GIC's target-list limitations. 32-bit KVM hosts currently
+     * always create clusters of 4 CPUs, but that is expected to
+     * change when they gain support for gicv3. When KVM is enabled
+     * it will override the changes we make here, therefore our
+     * purposes are to make TCG consistent (with 64-bit KVM hosts)
+     * and to improve SGI efficiency.
+     */
+    if (vms->gic_version == VIRT_GIC_VERSION_2) {
+        clustersz = GIC_TARGETLIST_BITS;
+    } else {
+        clustersz = GICV3_TARGETLIST_BITS;
     }
+
     return arm_build_mp_affinity(idx, clustersz);
 }
 
-- 
2.43.0

[PULL 11/32] hw/arm/virt: Remove deprecated virt-2.7 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 9d82cf78b0e..a2a213717cc 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3649,16 +3649,3 @@ static void virt_machine_2_8_options(MachineClass *mc)
     vmc->claim_edge_triggered_timers = true;
 }
 DEFINE_VIRT_MACHINE(2, 8)
-
-static void virt_machine_2_7_options(MachineClass *mc)
-{
-    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
-
-    virt_machine_2_8_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
-    /* ITS was introduced with 2.8 */
-    vmc->no_its = true;
-    /* Stick with 1K pages for migration compatibility */
-    mc->minimum_page_bits = 0;
-}
-DEFINE_VIRT_MACHINE(2, 7)
-- 
2.43.0

[PULL 12/32] hw/arm/virt: Remove VirtMachineClass::no_its field

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The VirtMachineClass::no_its field was only used by
virt-2.7 machine, which got removed. Remove it and
simplify virt_instance_init() and virt_acpi_build().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h    |  1 -
 hw/arm/virt-acpi-build.c |  5 ++---
 hw/arm/virt.c            | 16 ++++++----------
 3 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 5d3b25509ff..463ac09615e 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -117,7 +117,6 @@ typedef enum VirtGICType {
 
 struct VirtMachineClass {
     MachineClass parent;
-    bool no_its;
     bool no_tcg_its;
     bool claim_edge_triggered_timers;
     bool smbios_old_sys_ver;
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 3ac8f8e1786..1c8b61f9f8a 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -670,7 +670,6 @@ static void
 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 {
     int i;
-    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
     const MemMapEntry *memmap = vms->memmap;
     AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id,
                         .oem_table_id = vms->oem_table_id };
@@ -741,7 +740,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
                                           memmap[VIRT_HIGH_GIC_REDIST2].size);
         }
 
-        if (its_class_name() && !vmc->no_its) {
+        if (its_class_name()) {
             /*
              * ACPI spec, Revision 6.0 Errata A
              * (original 6.0 definition has invalid Length)
@@ -973,7 +972,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
                           vms->oem_table_id);
     }
 
-    if (its_class_name() && !vmc->no_its) {
+    if (its_class_name()) {
         acpi_add_table(table_offsets, tables_blob);
         build_iort(tables_blob, tables->linker, vms);
     }
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a2a213717cc..9c4efcd8556 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3347,17 +3347,13 @@ static void virt_instance_init(Object *obj)
     vms->highmem_mmio = true;
     vms->highmem_redists = true;
 
-    if (vmc->no_its) {
-        vms->its = false;
-    } else {
-        /* Default allows ITS instantiation */
-        vms->its = true;
+    /* Default allows ITS instantiation */
+    vms->its = true;
 
-        if (vmc->no_tcg_its) {
-            vms->tcg_its = false;
-        } else {
-            vms->tcg_its = true;
-        }
+    if (vmc->no_tcg_its) {
+        vms->tcg_its = false;
+    } else {
+        vms->tcg_its = true;
     }
 
     /* Default disallows iommu instantiation */
-- 
2.43.0

[PULL 13/32] hw/arm/virt: Remove deprecated virt-2.8 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 9c4efcd8556..4ef3f043a21 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3632,16 +3632,3 @@ static void virt_machine_2_9_options(MachineClass *mc)
     compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
 }
 DEFINE_VIRT_MACHINE(2, 9)
-
-static void virt_machine_2_8_options(MachineClass *mc)
-{
-    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
-
-    virt_machine_2_9_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
-    /* For 2.8 and earlier we falsely claimed in the DT that
-     * our timers were edge-triggered, not level-triggered.
-     */
-    vmc->claim_edge_triggered_timers = true;
-}
-DEFINE_VIRT_MACHINE(2, 8)
-- 
2.43.0

[PULL 14/32] hw/arm/virt: Remove VirtMachineClass::claim_edge_triggered_timers field

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The VirtMachineClass::claim_edge_triggered_timers field
was only used by virt-2.8 machine, which got removed.
Remove it and simplify fdt_add_timer_nodes() and build_gtdt().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h    | 1 -
 hw/arm/virt-acpi-build.c | 5 +----
 hw/arm/virt.c            | 5 -----
 3 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 463ac09615e..9c531e28d04 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -118,7 +118,6 @@ typedef enum VirtGICType {
 struct VirtMachineClass {
     MachineClass parent;
     bool no_tcg_its;
-    bool claim_edge_triggered_timers;
     bool smbios_old_sys_ver;
     bool no_highmem_compact;
     bool no_highmem_ecam;
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 1c8b61f9f8a..7e8e0f0298d 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -537,15 +537,12 @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 static void
 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 {
-    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
     /*
      * Table 5-117 Flag Definitions
      * set only "Timer interrupt Mode" and assume "Timer Interrupt
      * polarity" bit as '0: Interrupt is Active high'
      */
-    uint32_t irqflags = vmc->claim_edge_triggered_timers ?
-        1 : /* Interrupt is Edge triggered */
-        0;  /* Interrupt is Level triggered  */
+    const uint32_t irqflags = 0;  /* Interrupt is Level triggered  */
     AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
                         .oem_table_id = vms->oem_table_id };
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4ef3f043a21..13cbd2275ef 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -370,14 +370,9 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
      * the correct information.
      */
     ARMCPU *armcpu;
-    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
     MachineState *ms = MACHINE(vms);
 
-    if (vmc->claim_edge_triggered_timers) {
-        irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
-    }
-
     if (vms->gic_version == VIRT_GIC_VERSION_2) {
         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
-- 
2.43.0

[PULL 15/32] hw/arm/virt: Remove deprecated virt-2.9 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 13cbd2275ef..1c84297fab9 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3620,10 +3620,3 @@ static void virt_machine_2_10_options(MachineClass *mc)
     mc->ignore_memory_transaction_failures = true;
 }
 DEFINE_VIRT_MACHINE(2, 10)
-
-static void virt_machine_2_9_options(MachineClass *mc)
-{
-    virt_machine_2_10_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
-}
-DEFINE_VIRT_MACHINE(2, 9)
-- 
2.43.0

[PULL 16/32] hw/arm/virt: Remove deprecated virt-2.10 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 1c84297fab9..6e10b2b0857 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3611,12 +3611,3 @@ static void virt_machine_2_11_options(MachineClass *mc)
     vmc->smbios_old_sys_ver = true;
 }
 DEFINE_VIRT_MACHINE(2, 11)
-
-static void virt_machine_2_10_options(MachineClass *mc)
-{
-    virt_machine_2_11_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
-    /* before 2.11 we never faulted accesses to bad addresses */
-    mc->ignore_memory_transaction_failures = true;
-}
-DEFINE_VIRT_MACHINE(2, 10)
-- 
2.43.0

[PULL 17/32] hw/arm/virt: Remove deprecated virt-2.11 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 6e10b2b0857..4b21f3226f9 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3601,13 +3601,3 @@ static void virt_machine_2_12_options(MachineClass *mc)
     mc->max_cpus = 255;
 }
 DEFINE_VIRT_MACHINE(2, 12)
-
-static void virt_machine_2_11_options(MachineClass *mc)
-{
-    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
-
-    virt_machine_2_12_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
-    vmc->smbios_old_sys_ver = true;
-}
-DEFINE_VIRT_MACHINE(2, 11)
-- 
2.43.0

[PULL 18/32] hw/arm/virt: Remove VirtMachineClass::smbios_old_sys_ver field

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The VirtMachineClass::smbios_old_sys_ver field was
only used by virt-2.11 machine, which got removed.
Remove it and simplify virt_build_smbios().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h | 1 -
 hw/arm/virt.c         | 4 +---
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 9c531e28d04..b2cc012a402 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -118,7 +118,6 @@ typedef enum VirtGICType {
 struct VirtMachineClass {
     MachineClass parent;
     bool no_tcg_its;
-    bool smbios_old_sys_ver;
     bool no_highmem_compact;
     bool no_highmem_ecam;
     bool no_ged;   /* Machines < 4.2 have no support for ACPI GED device */
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4b21f3226f9..3488bc4fb9d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1699,7 +1699,6 @@ static void virt_build_smbios(VirtMachineState *vms)
 {
     MachineClass *mc = MACHINE_GET_CLASS(vms);
     MachineState *ms = MACHINE(vms);
-    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
     uint8_t *smbios_tables, *smbios_anchor;
     size_t smbios_tables_len, smbios_anchor_len;
     struct smbios_phys_mem_area mem_array;
@@ -1709,8 +1708,7 @@ static void virt_build_smbios(VirtMachineState *vms)
         product = "KVM Virtual Machine";
     }
 
-    smbios_set_defaults("QEMU", product,
-                        vmc->smbios_old_sys_ver ? "1.0" : mc->name);
+    smbios_set_defaults("QEMU", product, mc->name);
 
     /* build the array of physical mem area from base_memmap */
     mem_array.address = vms->memmap[VIRT_MEM].base;
-- 
2.43.0

[PULL 19/32] hw/arm/virt: Remove deprecated virt-2.12 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 3488bc4fb9d..d047983c80e 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3588,14 +3588,3 @@ static void virt_machine_3_0_options(MachineClass *mc)
     compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
 }
 DEFINE_VIRT_MACHINE(3, 0)
-
-static void virt_machine_2_12_options(MachineClass *mc)
-{
-    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
-
-    virt_machine_3_0_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
-    vmc->no_highmem_ecam = true;
-    mc->max_cpus = 255;
-}
-DEFINE_VIRT_MACHINE(2, 12)
-- 
2.43.0

[PULL 20/32] hw/arm/virt: Remove VirtMachineClass::no_highmem_ecam field

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The VirtMachineClass::no_highmem_ecam field was only
used by virt-2.12 machine, which got removed. Remove it
and simplify virt_instance_init().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h | 1 -
 hw/arm/virt.c         | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index b2cc012a402..9a1b0f53d21 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -119,7 +119,6 @@ struct VirtMachineClass {
     MachineClass parent;
     bool no_tcg_its;
     bool no_highmem_compact;
-    bool no_highmem_ecam;
     bool no_ged;   /* Machines < 4.2 have no support for ACPI GED device */
     bool kvm_no_adjvtime;
     bool no_kvm_steal_time;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d047983c80e..bd1a68673a7 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3336,7 +3336,7 @@ static void virt_instance_init(Object *obj)
     vms->highmem_compact = !vmc->no_highmem_compact;
     vms->gic_version = VIRT_GIC_VERSION_NOSEL;
 
-    vms->highmem_ecam = !vmc->no_highmem_ecam;
+    vms->highmem_ecam = true;
     vms->highmem_mmio = true;
     vms->highmem_redists = true;
 
-- 
2.43.0

[PULL 21/32] tests/functional: Add test for imx8mp-evk board with USDHC coverage

[Peter Maydell]

From: Bernhard Beschow <shentey@gmail.com>

Introduce a functional test which boots Debian 12 on the imx8mp-evk board. Since
the root filesystem resides on an SD card, the test also verifies the basic
operation of the USDHC.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20250409202630.19667-1-shentey@gmail.com
[PMM: added extra blank line as suggested by thuth;
 set timeout to 240s]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS                                 |  1 +
 tests/functional/meson.build                |  2 +
 tests/functional/test_aarch64_imx8mp_evk.py | 67 +++++++++++++++++++++
 3 files changed, 70 insertions(+)
 create mode 100755 tests/functional/test_aarch64_imx8mp_evk.py

diff --git a/MAINTAINERS b/MAINTAINERS
index e748b6375ee..ba702549466 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -843,6 +843,7 @@ F: include/hw/arm/fsl-imx8mp.h
 F: include/hw/misc/imx8mp_*.h
 F: include/hw/pci-host/fsl_imx8m_phy.h
 F: docs/system/arm/imx8mp-evk.rst
+F: tests/functional/test_aarch64_imx8mp_evk.py
 F: tests/qtest/rs5c372-test.c
 
 MPS2 / MPS3
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index ab9df03b1f6..52b4706cfe8 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -13,6 +13,7 @@ endif
 test_timeouts = {
   'aarch64_aspeed_ast2700' : 600,
   'aarch64_aspeed_ast2700fc' : 600,
+  'aarch64_imx8mp_evk' : 240,
   'aarch64_raspi4' : 480,
   'aarch64_reverse_debug' : 180,
   'aarch64_rme_virt' : 1200,
@@ -82,6 +83,7 @@ tests_aarch64_system_quick = [
 tests_aarch64_system_thorough = [
   'aarch64_aspeed_ast2700',
   'aarch64_aspeed_ast2700fc',
+  'aarch64_imx8mp_evk',
   'aarch64_raspi3',
   'aarch64_raspi4',
   'aarch64_replay',
diff --git a/tests/functional/test_aarch64_imx8mp_evk.py b/tests/functional/test_aarch64_imx8mp_evk.py
new file mode 100755
index 00000000000..638bf9e1310
--- /dev/null
+++ b/tests/functional/test_aarch64_imx8mp_evk.py
@@ -0,0 +1,67 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots a Linux kernel and checks the console
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import LinuxKernelTest, Asset
+
+
+class Imx8mpEvkMachine(LinuxKernelTest):
+
+    ASSET_IMAGE = Asset(
+        ('https://cloud.debian.org/images/cloud/bookworm/20231210-1590/'
+         'debian-12-generic-arm64-20231210-1590.tar.xz'),
+        '7ebf1577b32d5af6204df74b54ca2e4675de9b5a9fa14f3ff70b88eeb7b3b359')
+
+    KERNEL_OFFSET = 0x51000000
+    KERNEL_SIZE = 32622528
+    INITRD_OFFSET = 0x76000000
+    INITRD_SIZE = 30987766
+    DTB_OFFSET = 0x64F51000
+    DTB_SIZE = 45 * 1024
+
+    def extract(self, in_path, out_path, offset, size):
+        try:
+            with open(in_path, "rb") as source:
+                source.seek(offset)
+                data = source.read(size)
+            with open(out_path, "wb") as target:
+                target.write(data)
+        except (IOError, ValueError) as e:
+            self.log.error(f"Failed to extract {out_path}: {e}")
+            raise
+
+    def setUp(self):
+        super().setUp()
+
+        self.image_path = self.scratch_file("disk.raw")
+        self.kernel_path = self.scratch_file("linux")
+        self.initrd_path = self.scratch_file("initrd.zstd")
+        self.dtb_path = self.scratch_file("imx8mp-evk.dtb")
+
+        self.archive_extract(self.ASSET_IMAGE)
+        self.extract(self.image_path, self.kernel_path,
+                     self.KERNEL_OFFSET, self.KERNEL_SIZE)
+        self.extract(self.image_path, self.initrd_path,
+                     self.INITRD_OFFSET, self.INITRD_SIZE)
+        self.extract(self.image_path, self.dtb_path,
+                     self.DTB_OFFSET, self.DTB_SIZE)
+
+    def test_aarch64_imx8mp_evk_usdhc(self):
+        self.set_machine('imx8mp-evk')
+        self.vm.set_console(console_index=1)
+        self.vm.add_args('-m', '2G',
+                         '-smp', '4',
+                         '-kernel', self.kernel_path,
+                         '-initrd', self.initrd_path,
+                         '-dtb', self.dtb_path,
+                         '-append', 'root=/dev/mmcblk2p1',
+                         '-drive', f'file={self.image_path},if=sd,bus=2,'
+                                    'format=raw,id=mmcblk2,snapshot=on')
+
+        self.vm.launch()
+        self.wait_for_console_pattern('Welcome to ')
+
+if __name__ == '__main__':
+    LinuxKernelTest.main()
-- 
2.43.0

[PULL 22/32] hw/arm: Attach PSPI module to NPCM8XX SoC

[Peter Maydell]

From: Tim Lee <timlee660101@gmail.com>

Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices. Attach it to the NPCM8XX.

Tested:
NPCM8XX PSPI driver probed successfully from dmesg log.

Signed-off-by: Tim Lee <timlee660101@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20250414020629.1867106-1-timlee660101@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/npcm8xx.h |  2 ++
 hw/arm/npcm8xx.c         | 11 ++++++++++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/npcm8xx.h b/include/hw/arm/npcm8xx.h
index 9812e6fa7ec..3436abff998 100644
--- a/include/hw/arm/npcm8xx.h
+++ b/include/hw/arm/npcm8xx.h
@@ -36,6 +36,7 @@
 #include "hw/usb/hcd-ehci.h"
 #include "hw/usb/hcd-ohci.h"
 #include "target/arm/cpu.h"
+#include "hw/ssi/npcm_pspi.h"
 
 #define NPCM8XX_MAX_NUM_CPUS    (4)
 
@@ -99,6 +100,7 @@ struct NPCM8xxState {
     OHCISysBusState     ohci[2];
     NPCM7xxFIUState     fiu[3];
     NPCM7xxSDHCIState   mmc;
+    NPCMPSPIState       pspi;
 };
 
 struct NPCM8xxClass {
diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
index 5cc67b132fc..d7ee306de7a 100644
--- a/hw/arm/npcm8xx.c
+++ b/hw/arm/npcm8xx.c
@@ -67,6 +67,9 @@
 /* SDHCI Modules */
 #define NPCM8XX_MMC_BA          0xf0842000
 
+/* PSPI Modules */
+#define NPCM8XX_PSPI_BA         0xf0201000
+
 /* Run PLL1 at 1600 MHz */
 #define NPCM8XX_PLLCON1_FIXUP_VAL   0x00402101
 /* Run the CPU from PLL1 and UART from PLL2 */
@@ -83,6 +86,7 @@ enum NPCM8xxInterrupt {
     NPCM8XX_PECI_IRQ            = 6,
     NPCM8XX_KCS_HIB_IRQ         = 9,
     NPCM8XX_MMC_IRQ             = 26,
+    NPCM8XX_PSPI_IRQ            = 28,
     NPCM8XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
     NPCM8XX_TIMER1_IRQ,
     NPCM8XX_TIMER2_IRQ,
@@ -441,6 +445,7 @@ static void npcm8xx_init(Object *obj)
     }
 
     object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
+    object_initialize_child(obj, "pspi", &s->pspi, TYPE_NPCM_PSPI);
 }
 
 static void npcm8xx_realize(DeviceState *dev, Error **errp)
@@ -705,6 +710,11 @@ static void npcm8xx_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
             npcm8xx_irq(s, NPCM8XX_MMC_IRQ));
 
+    /* PSPI */
+    sysbus_realize(SYS_BUS_DEVICE(&s->pspi), &error_abort);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->pspi), 0, NPCM8XX_PSPI_BA);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->pspi), 0,
+            npcm8xx_irq(s, NPCM8XX_PSPI_IRQ));
 
     create_unimplemented_device("npcm8xx.shm",          0xc0001000,   4 * KiB);
     create_unimplemented_device("npcm8xx.gicextra",     0xdfffa000,  24 * KiB);
@@ -720,7 +730,6 @@ static void npcm8xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm8xx.siox[1]",      0xf0101000,   4 * KiB);
     create_unimplemented_device("npcm8xx.siox[2]",      0xf0102000,   4 * KiB);
     create_unimplemented_device("npcm8xx.tmps",         0xf0188000,   4 * KiB);
-    create_unimplemented_device("npcm8xx.pspi",         0xf0201000,   4 * KiB);
     create_unimplemented_device("npcm8xx.viru1",        0xf0204000,   4 * KiB);
     create_unimplemented_device("npcm8xx.viru2",        0xf0205000,   4 * KiB);
     create_unimplemented_device("npcm8xx.jtm1",         0xf0208000,   4 * KiB);
-- 
2.43.0

[PULL 23/32] target/arm: Don't assert() for ISB/SB inside IT block

[Peter Maydell]

If the guest code has an ISB or SB insn inside an IT block, we
generate incorrect code which trips a TCG assertion:

qemu-system-arm: ../tcg/tcg-op.c:3343: void tcg_gen_goto_tb(unsigned int): Assertion `(tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0' failed.

This is because we call gen_goto_tb(dc, 1, ...) twice:

 brcond_i32 ZF,$0x0,ne,$L1
 add_i32 pc,pc,$0x4
 goto_tb $0x1
 exit_tb $0x73d948001b81
 set_label $L1
 add_i32 pc,pc,$0x4
 goto_tb $0x1
 exit_tb $0x73d948001b81

Both calls are in arm_tr_tb_stop(), one for the
DISAS_NEXT/DISAS_TOO_MANY handling, and one for the dc->condjump
condition-failed codepath.  The DISAS_NEXT handling doesn't have this
problem because arm_post_translate_insn() does the handling of "emit
the label for the condition-failed conditional execution" and so
arm_tr_tb_stop() doesn't have dc->condjump set.  But for
DISAS_TOO_MANY we don't do that.

Fix the bug by making arm_post_translate_insn() handle the
DISAS_TOO_MANY case.  This only affects the SB and ISB insns when
used in Thumb mode inside an IT block: only these insns specifically
set is_jmp to TOO_MANY, and their A32 encodings are unconditional.

For the major TOO_MANY case (breaking the TB because it would cross a
page boundary) we do that check and set is_jmp to TOO_MANY only after
the call to arm_post_translate_insn(); so arm_post_translate_insn()
sees is_jmp == DISAS_NEXT, and  we emit the correct code for that
situation.

With this fix we generate the somewhat more sensible set of TCG ops:
 brcond_i32 ZF,$0x0,ne,$L1
 set_label $L1
 add_i32 pc,pc,$0x4
 goto_tb $0x1
 exit_tb $0x7c5434001b81

(NB: the TCG optimizer doesn't optimize out the jump-to-next, but
we can't really avoid emitting it because we don't know at the
point we're emitting the handling for the condexec check whether
this insn is going to happen to be a nop for us or not.)

Cc: qemu-stable@nongnu.org
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2942
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250501125544.727038-1-peter.maydell@linaro.org
---
 target/arm/tcg/translate.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 88df9c482ab..e773ab72685 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -7760,7 +7760,8 @@ static bool arm_check_ss_active(DisasContext *dc)
 
 static void arm_post_translate_insn(DisasContext *dc)
 {
-    if (dc->condjmp && dc->base.is_jmp == DISAS_NEXT) {
+    if (dc->condjmp &&
+        (dc->base.is_jmp == DISAS_NEXT || dc->base.is_jmp == DISAS_TOO_MANY)) {
         if (dc->pc_save != dc->condlabel.pc_save) {
             gen_update_pc(dc, dc->condlabel.pc_save - dc->pc_save);
         }
-- 
2.43.0

[PULL 24/32] docs: Don't define duplicate label in qemu-block-drivers.rst.inc

[Peter Maydell]

Sphinx requires that labels within documents are unique across the
whole manual.  This is because the "create a hyperlink" directive
specifies only the name of the label, not a filename+label.  Some
Sphinx versions will warn about duplicate labels, but even if there
is no warning there is still an ambiguity and no guarantee that the
hyperlink will be created to the right target.

For QEMU this is awkward, because we have various .rst.inc fragments
which we include into multiple .rst files.  If you define a label in
the .rst.inc file then it will be a duplicate label.  We have mostly
worked around this by not putting labels into those .rst.inc files,
or by adding "insert a label" functionality into the hxtool extension
(see commit 1eeb432a953b0 "doc/sphinx/hxtool.py: add optional label
argument to SRST directive").

Unfortunately in commit 7f6314427e78 ("docs/devel: add a codebase
section") we accidentally added a duplicate label, because not all
Sphinx versions warn about the mistake.

In this case the link was only from the developer docs codebase
summary, so as the simplest fix for the stable branch, we drop
the link entirely.

Cc: qemu-stable@nongnu.org
Fixes: 1eeb432a953b0 "doc/sphinx/hxtool.py: add optional label argument to SRST directive"
Reported-by: Dario Faggioli <dfaggioli@suse.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20250501093126.716667-1-peter.maydell@linaro.org
---
 docs/devel/codebase.rst                | 2 +-
 docs/system/qemu-block-drivers.rst.inc | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/docs/devel/codebase.rst b/docs/devel/codebase.rst
index 40273e7d31e..2a3143787a6 100644
--- a/docs/devel/codebase.rst
+++ b/docs/devel/codebase.rst
@@ -116,7 +116,7 @@ yet, so sometimes the source code is all you have.
 * `monitor <https://gitlab.com/qemu-project/qemu/-/tree/master/monitor>`_:
   `Monitor <QEMU monitor>` implementation (HMP & QMP).
 * `nbd <https://gitlab.com/qemu-project/qemu/-/tree/master/nbd>`_:
-  QEMU `NBD (Network Block Device) <nbd>` server.
+  QEMU NBD (Network Block Device) server.
 * `net <https://gitlab.com/qemu-project/qemu/-/tree/master/net>`_:
   Network (host) support.
 * `pc-bios <https://gitlab.com/qemu-project/qemu/-/tree/master/pc-bios>`_:
diff --git a/docs/system/qemu-block-drivers.rst.inc b/docs/system/qemu-block-drivers.rst.inc
index cfe1acb78ae..384e95ba765 100644
--- a/docs/system/qemu-block-drivers.rst.inc
+++ b/docs/system/qemu-block-drivers.rst.inc
@@ -500,8 +500,6 @@ What you should *never* do:
 - expect it to work when loadvm'ing
 - write to the FAT directory on the host system while accessing it with the guest system
 
-.. _nbd:
-
 NBD access
 ~~~~~~~~~~
 
-- 
2.43.0

[PULL 25/32] target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET

[Peter Maydell]

Our KVM code includes backwards compatibility support for ancient
kernels which don't support the KVM_ARM_PREFERRED_TARGET ioctl.  This
ioctl was introduced in kernel commit 42c4e0c77ac91 in September
2013 and is in v3.12, so it's reasonable to assume it's present.

(We already dropped support for kernels without KVM_CAP_DEVICE_CTRL,
a feature added to the kernel in April 2013, in our commit
84f298ea3e; so there are only about six months' worth of kernels,
from v3.9 to v3.11, that we don't already fail to run on and that
this commit is dropping handling for.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250318114222.1018200-1-peter.maydell@linaro.org
---
 target/arm/kvm_arm.h      |  7 +----
 target/arm/arm-qmp-cmds.c |  2 +-
 target/arm/kvm.c          | 55 ++++++---------------------------------
 3 files changed, 10 insertions(+), 54 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 05c3de8cd46..5f17fc2f3d5 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -97,10 +97,6 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu);
 #ifdef CONFIG_KVM
 /**
  * kvm_arm_create_scratch_host_vcpu:
- * @cpus_to_try: array of QEMU_KVM_ARM_TARGET_* values (terminated with
- * QEMU_KVM_ARM_TARGET_NONE) to try as fallback if the kernel does not
- * know the PREFERRED_TARGET ioctl. Passing NULL is the same as passing
- * an empty array.
  * @fdarray: filled in with kvmfd, vmfd, cpufd file descriptors in that order
  * @init: filled in with the necessary values for creating a host
  * vcpu. If NULL is provided, will not init the vCPU (though the cpufd
@@ -113,8 +109,7 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu);
  * Returns: true on success (and fdarray and init are filled in),
  * false on failure (and fdarray and init are not valid).
  */
-bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
-                                      int *fdarray,
+bool kvm_arm_create_scratch_host_vcpu(int *fdarray,
                                       struct kvm_vcpu_init *init);
 
 /**
diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c
index 883c0a0e8cc..a1a944adb43 100644
--- a/target/arm/arm-qmp-cmds.c
+++ b/target/arm/arm-qmp-cmds.c
@@ -46,7 +46,7 @@ static inline void gic_cap_kvm_probe(GICCapability *v2, GICCapability *v3)
 #ifdef CONFIG_KVM
     int fdarray[3];
 
-    if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, NULL)) {
+    if (!kvm_arm_create_scratch_host_vcpu(fdarray, NULL)) {
         return;
     }
 
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 97de8c7e939..9c62d12b233 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -100,8 +100,7 @@ static int kvm_arm_vcpu_finalize(ARMCPU *cpu, int feature)
     return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_FINALIZE, &feature);
 }
 
-bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
-                                      int *fdarray,
+bool kvm_arm_create_scratch_host_vcpu(int *fdarray,
                                       struct kvm_vcpu_init *init)
 {
     int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1;
@@ -150,40 +149,13 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
         struct kvm_vcpu_init preferred;
 
         ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred);
-        if (!ret) {
-            init->target = preferred.target;
+        if (ret < 0) {
+            goto err;
         }
+        init->target = preferred.target;
     }
-    if (ret >= 0) {
-        ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
-        if (ret < 0) {
-            goto err;
-        }
-    } else if (cpus_to_try) {
-        /* Old kernel which doesn't know about the
-         * PREFERRED_TARGET ioctl: we know it will only support
-         * creating one kind of guest CPU which is its preferred
-         * CPU type.
-         */
-        struct kvm_vcpu_init try;
-
-        while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
-            try.target = *cpus_to_try++;
-            memcpy(try.features, init->features, sizeof(init->features));
-            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, &try);
-            if (ret >= 0) {
-                break;
-            }
-        }
-        if (ret < 0) {
-            goto err;
-        }
-        init->target = try.target;
-    } else {
-        /* Treat a NULL cpus_to_try argument the same as an empty
-         * list, which means we will fail the call since this must
-         * be an old kernel which doesn't support PREFERRED_TARGET.
-         */
+    ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
+    if (ret < 0) {
         goto err;
     }
 
@@ -259,17 +231,6 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     uint64_t features = 0;
     int err;
 
-    /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
-     * we know these will only support creating one kind of guest CPU,
-     * which is its preferred CPU type. Fortunately these old kernels
-     * support only a very limited number of CPUs.
-     */
-    static const uint32_t cpus_to_try[] = {
-        KVM_ARM_TARGET_AEM_V8,
-        KVM_ARM_TARGET_FOUNDATION_V8,
-        KVM_ARM_TARGET_CORTEX_A57,
-        QEMU_KVM_ARM_TARGET_NONE
-    };
     /*
      * target = -1 informs kvm_arm_create_scratch_host_vcpu()
      * to use the preferred target
@@ -300,7 +261,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         features |= 1ULL << ARM_FEATURE_PMU;
     }
 
-    if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
+    if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) {
         return false;
     }
 
@@ -1835,7 +1796,7 @@ uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu)
 
         probed = true;
 
-        if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) {
+        if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) {
             error_report("failed to create scratch VCPU with SVE enabled");
             abort();
         }
-- 
2.43.0

[PULL 26/32] hw/pci-host/designware: Remove unused include

[Peter Maydell]

From: Bernhard Beschow <shentey@gmail.com>

The DEFINE_TYPES() macro doesn't need the qemu/module.h include.

Fixes: 13a07eb146c8 ("hw/pci-host/designware: Declare CPU QOM types using DEFINE_TYPES() macro")
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250501183445.2389-2-shentey@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/pci-host/designware.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 183f838392c..b4bff145794 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -20,7 +20,6 @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
-#include "qemu/module.h"
 #include "qemu/log.h"
 #include "qemu/bitops.h"
 #include "hw/pci/msi.h"
-- 
2.43.0

[PULL 27/32] hw/pci-host/designware: Fix viewport configuration

[Peter Maydell]

From: Bernhard Beschow <shentey@gmail.com>

Commit 6970f91ac781, "hw/pci-host/designware: Use deposit/extract
API" accidentally introduced a copy-and-paste error, causing Linux
6.14 to hang when initializing the PCIe bridge on the imx8mp-evk
machine.  This fix corrects the error.

Fixes: 6970f91ac781 ("hw/pci-host/designware: Use deposit/extract API")
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250501183445.2389-3-shentey@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/pci-host/designware.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index b4bff145794..f6e49ce9b8d 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -348,14 +348,14 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
 
     case DESIGNWARE_PCIE_ATU_LOWER_BASE:
     case DESIGNWARE_PCIE_ATU_UPPER_BASE:
-        viewport->base = deposit64(root->msi.base,
+        viewport->base = deposit64(viewport->base,
                                    address == DESIGNWARE_PCIE_ATU_LOWER_BASE
                                    ? 0 : 32, 32, val);
         break;
 
     case DESIGNWARE_PCIE_ATU_LOWER_TARGET:
     case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
-        viewport->target = deposit64(root->msi.base,
+        viewport->target = deposit64(viewport->target,
                                      address == DESIGNWARE_PCIE_ATU_LOWER_TARGET
                                      ? 0 : 32, 32, val);
         break;
-- 
2.43.0

[PULL 28/32] hw/gpio/imx_gpio: Fix interpretation of GDIR polarity

[Peter Maydell]

From: Bernhard Beschow <shentey@gmail.com>

According to the i.MX 8M Plus reference manual, a GPIO pin is
configured as an output when the corresponding bit in the GDIR
register is set.  The function imx_gpio_set_int_line() is intended to
be a no-op if the pin is configured as an output, returning early in
such cases.  However, it inverts the condition.  Fix this by
returning early when the bit is set.

cc: qemu-stable@nongnu.org
Fixes: f44272809779 ("i.MX: Add GPIO device")
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250501183445.2389-4-shentey@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/imx_gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c
index f23c52af26d..450ece45482 100644
--- a/hw/gpio/imx_gpio.c
+++ b/hw/gpio/imx_gpio.c
@@ -72,7 +72,7 @@ static void imx_gpio_update_int(IMXGPIOState *s)
 static void imx_gpio_set_int_line(IMXGPIOState *s, int line, IMXGPIOLevel level)
 {
     /* if this signal isn't configured as an input signal, nothing to do */
-    if (!extract32(s->gdir, line, 1)) {
+    if (extract32(s->gdir, line, 1)) {
         return;
     }
 
-- 
2.43.0

[PULL 29/32] hw/arm/virt: Update comment about Multiprocessor Affinity Register

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Support on ARMv7 has been dropped in commit 82bf7ae84ce
("target/arm: Remove KVM support for 32-bit Arm hosts").
Update the comment in virt_cpu_mp_affinity() to avoid
mentioning it.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250429153907.31866-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index bd1a68673a7..03fef07c9da 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1766,12 +1766,7 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
     uint8_t clustersz;
 
     /*
-     * Adjust MPIDR like 64-bit KVM hosts, which incorporate the
-     * GIC's target-list limitations. 32-bit KVM hosts currently
-     * always create clusters of 4 CPUs, but that is expected to
-     * change when they gain support for gicv3. When KVM is enabled
-     * it will override the changes we make here, therefore our
-     * purposes are to make TCG consistent (with 64-bit KVM hosts)
+     * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts)
      * and to improve SGI efficiency.
      */
     if (vms->gic_version == VIRT_GIC_VERSION_2) {
-- 
2.43.0

[PULL 30/32] hw/arm/virt: Remove deprecated virt-3.0 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250429153907.31866-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 03fef07c9da..1e4841f036c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3576,10 +3576,3 @@ static void virt_machine_3_1_options(MachineClass *mc)
     compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
 }
 DEFINE_VIRT_MACHINE(3, 1)
-
-static void virt_machine_3_0_options(MachineClass *mc)
-{
-    virt_machine_3_1_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
-}
-DEFINE_VIRT_MACHINE(3, 0)
-- 
2.43.0

[PULL 31/32] hw/arm/virt: Remove deprecated virt-3.1 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250429153907.31866-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 1e4841f036c..61fd8557683 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3569,10 +3569,3 @@ static void virt_machine_4_0_options(MachineClass *mc)
     compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
 }
 DEFINE_VIRT_MACHINE(4, 0)
-
-static void virt_machine_3_1_options(MachineClass *mc)
-{
-    virt_machine_4_0_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
-}
-DEFINE_VIRT_MACHINE(3, 1)
-- 
2.43.0

[PULL 32/32] hw/arm/virt: Remove deprecated virt-4.0 machine

[Peter Maydell]

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This machine has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250429153907.31866-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 61fd8557683..9a6cd085a37 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3562,10 +3562,3 @@ static void virt_machine_4_1_options(MachineClass *mc)
     mc->auto_enable_numa_with_memhp = false;
 }
 DEFINE_VIRT_MACHINE(4, 1)
-
-static void virt_machine_4_0_options(MachineClass *mc)
-{
-    virt_machine_4_1_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
-}
-DEFINE_VIRT_MACHINE(4, 0)
-- 
2.43.0

Re: [PULL 00/32] target-arm queue

[Stefan Hajnoczi]

On Tue, May 6, 2025 at 10:52 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Now I'm back from holiday, here's a target-arm pullreq :-)
>
> thanks
> -- PMM
>
> The following changes since commit a9e0c9c0f14e19d23443ac24c8080b4708d2eab8:
>
>   Merge tag 'pull-9p-20250505' of https://github.com/cschoenebeck/qemu into staging (2025-05-05 11:26:59 -0400)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250506
>
> for you to fetch changes up to 607e1208b53ac713a76d158f4abc4cd2e8870051:
>
>   hw/arm/virt: Remove deprecated virt-4.0 machine (2025-05-06 15:02:35 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC
>  * arm/hvf: fix crashes when using gdbstub
>  * target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug
>  * hw/arm/virt: Remove deprecated old versions of 'virt' machine
>  * tests/functional: Add test for imx8mp-evk board with USDHC coverage
>  * hw/arm: Attach PSPI module to NPCM8XX SoC
>  * target/arm: Don't assert() for ISB/SB inside IT block
>  * docs: Don't define duplicate label in qemu-block-drivers.rst.inc
>  * target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET
>  * hw/pci-host/designware: Fix viewport configuration
>  * hw/gpio/imx_gpio: Fix interpretation of GDIR polarity
>
> ----------------------------------------------------------------
> Bernhard Beschow (4):
>       tests/functional: Add test for imx8mp-evk board with USDHC coverage
>       hw/pci-host/designware: Remove unused include
>       hw/pci-host/designware: Fix viewport configuration
>       hw/gpio/imx_gpio: Fix interpretation of GDIR polarity
>
> Mads Ynddal (2):
>       hvf: avoid repeatedly setting trap debug for each cpu
>       hvf: only update sysreg from owning thread

Please take a look at the following aarch64 macOS CI failure:

../accel/hvf/hvf-all.c:61:54: error: unknown type name 'run_on_cpu_data'
61 | static void do_hvf_update_guest_debug(CPUState *cpu, run_on_cpu_data arg)
| ^
../accel/hvf/hvf-all.c:68:5: error: call to undeclared function
'run_on_cpu'; ISO C99 and later do not support implicit function
declarations [-Wimplicit-function-declaration]
68 | run_on_cpu(cpu, do_hvf_update_guest_debug, RUN_ON_CPU_NULL);
| ^
../accel/hvf/hvf-all.c:68:48: error: use of undeclared identifier
'RUN_ON_CPU_NULL'
68 | run_on_cpu(cpu, do_hvf_update_guest_debug, RUN_ON_CPU_NULL);
| ^
3 errors generated.

https://gitlab.com/qemu-project/qemu/-/jobs/9962088576

>
> Peter Maydell (3):
>       target/arm: Don't assert() for ISB/SB inside IT block
>       docs: Don't define duplicate label in qemu-block-drivers.rst.inc
>       target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET
>
> Philippe Mathieu-Daudé (17):
>       hw/arm/virt: Remove deprecated virt-2.6 machine
>       hw/arm/virt: Remove VirtMachineClass::no_pmu field
>       hw/arm/virt: Remove VirtMachineClass::disallow_affinity_adjustment
>       hw/arm/virt: Remove deprecated virt-2.7 machine
>       hw/arm/virt: Remove VirtMachineClass::no_its field
>       hw/arm/virt: Remove deprecated virt-2.8 machine
>       hw/arm/virt: Remove VirtMachineClass::claim_edge_triggered_timers field
>       hw/arm/virt: Remove deprecated virt-2.9 machine
>       hw/arm/virt: Remove deprecated virt-2.10 machine
>       hw/arm/virt: Remove deprecated virt-2.11 machine
>       hw/arm/virt: Remove VirtMachineClass::smbios_old_sys_ver field
>       hw/arm/virt: Remove deprecated virt-2.12 machine
>       hw/arm/virt: Remove VirtMachineClass::no_highmem_ecam field
>       hw/arm/virt: Update comment about Multiprocessor Affinity Register
>       hw/arm/virt: Remove deprecated virt-3.0 machine
>       hw/arm/virt: Remove deprecated virt-3.1 machine
>       hw/arm/virt: Remove deprecated virt-4.0 machine
>
> Pierrick Bouvier (4):
>       target/arm/ptw: extract arm_mmu_idx_to_security_space
>       target/arm/ptw: get current security_space for current mmu_idx
>       target/arm/ptw: extract arm_cpu_get_phys_page
>       target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug
>
> Tim Lee (2):
>       hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC
>       hw/arm: Attach PSPI module to NPCM8XX SoC
>
>  MAINTAINERS                                 |   1 +
>  docs/devel/codebase.rst                     |   2 +-
>  docs/system/qemu-block-drivers.rst.inc      |   2 -
>  include/hw/arm/npcm8xx.h                    |   2 +
>  include/hw/arm/virt.h                       |   6 --
>  target/arm/kvm_arm.h                        |   7 +-
>  accel/hvf/hvf-all.c                         |   7 +-
>  hw/arm/npcm8xx.c                            |  11 +-
>  hw/arm/npcm8xx_boards.c                     |   2 +-
>  hw/arm/virt-acpi-build.c                    |  10 +-
>  hw/arm/virt.c                               | 153 ++++------------------------
>  hw/gpio/imx_gpio.c                          |   2 +-
>  hw/pci-host/designware.c                    |   5 +-
>  target/arm/arm-qmp-cmds.c                   |   2 +-
>  target/arm/hvf/hvf.c                        |  27 ++---
>  target/arm/kvm.c                            |  55 ++--------
>  target/arm/ptw.c                            |  71 +++++++++----
>  target/arm/tcg/translate.c                  |   3 +-
>  tests/functional/meson.build                |   2 +
>  tests/functional/test_aarch64_imx8mp_evk.py |  67 ++++++++++++
>  20 files changed, 188 insertions(+), 249 deletions(-)
>  create mode 100755 tests/functional/test_aarch64_imx8mp_evk.py
>

Re: [PULL 00/32] target-arm queue

[Philippe Mathieu-Daudé]

On 7/5/25 16:05, Stefan Hajnoczi wrote:
> On Tue, May 6, 2025 at 10:52 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>>
>> Now I'm back from holiday, here's a target-arm pullreq :-)
>>
>> thanks
>> -- PMM
>>
>> The following changes since commit a9e0c9c0f14e19d23443ac24c8080b4708d2eab8:
>>
>>    Merge tag 'pull-9p-20250505' of https://github.com/cschoenebeck/qemu into staging (2025-05-05 11:26:59 -0400)
>>
>> are available in the Git repository at:
>>
>>    https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250506
>>
>> for you to fetch changes up to 607e1208b53ac713a76d158f4abc4cd2e8870051:
>>
>>    hw/arm/virt: Remove deprecated virt-4.0 machine (2025-05-06 15:02:35 +0100)
>>
>> ----------------------------------------------------------------
>> target-arm queue:
>>   * hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC
>>   * arm/hvf: fix crashes when using gdbstub
>>   * target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug
>>   * hw/arm/virt: Remove deprecated old versions of 'virt' machine
>>   * tests/functional: Add test for imx8mp-evk board with USDHC coverage
>>   * hw/arm: Attach PSPI module to NPCM8XX SoC
>>   * target/arm: Don't assert() for ISB/SB inside IT block
>>   * docs: Don't define duplicate label in qemu-block-drivers.rst.inc
>>   * target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET
>>   * hw/pci-host/designware: Fix viewport configuration
>>   * hw/gpio/imx_gpio: Fix interpretation of GDIR polarity
>>
>> ----------------------------------------------------------------
>> Bernhard Beschow (4):
>>        tests/functional: Add test for imx8mp-evk board with USDHC coverage
>>        hw/pci-host/designware: Remove unused include
>>        hw/pci-host/designware: Fix viewport configuration
>>        hw/gpio/imx_gpio: Fix interpretation of GDIR polarity
>>
>> Mads Ynddal (2):
>>        hvf: avoid repeatedly setting trap debug for each cpu
>>        hvf: only update sysreg from owning thread
> 
> Please take a look at the following aarch64 macOS CI failure:
> 
> ../accel/hvf/hvf-all.c:61:54: error: unknown type name 'run_on_cpu_data'
> 61 | static void do_hvf_update_guest_debug(CPUState *cpu, run_on_cpu_data arg)
> | ^
> ../accel/hvf/hvf-all.c:68:5: error: call to undeclared function
> 'run_on_cpu'; ISO C99 and later do not support implicit function
> declarations [-Wimplicit-function-declaration]
> 68 | run_on_cpu(cpu, do_hvf_update_guest_debug, RUN_ON_CPU_NULL);
> | ^
> ../accel/hvf/hvf-all.c:68:48: error: use of undeclared identifier
> 'RUN_ON_CPU_NULL'
> 68 | run_on_cpu(cpu, do_hvf_update_guest_debug, RUN_ON_CPU_NULL);
> | ^
> 3 errors generated.
> 
> https://gitlab.com/qemu-project/qemu/-/jobs/9962088576

"hvf: only update sysreg from owning thread" missing:

-- >8 --
diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c
index 3fc65d6b231..8c387fda24d 100644
--- a/accel/hvf/hvf-all.c
+++ b/accel/hvf/hvf-all.c
@@ -12,6 +12,7 @@
  #include "qemu/error-report.h"
  #include "system/hvf.h"
  #include "system/hvf_int.h"
+#include "hw/core/cpu.h"

  const char *hvf_return_string(hv_return_t ret)
  {
---

Re: [PULL 00/32] target-arm queue

[Philippe Mathieu-Daudé]

On 7/5/25 16:57, Philippe Mathieu-Daudé wrote:
> On 7/5/25 16:05, Stefan Hajnoczi wrote:
>> On Tue, May 6, 2025 at 10:52 AM Peter Maydell 
>> <peter.maydell@linaro.org> wrote:
>>>
>>> Now I'm back from holiday, here's a target-arm pullreq :-)
>>>
>>> thanks
>>> -- PMM
>>>
>>> The following changes since commit 
>>> a9e0c9c0f14e19d23443ac24c8080b4708d2eab8:
>>>
>>>    Merge tag 'pull-9p-20250505' of https://github.com/cschoenebeck/ 
>>> qemu into staging (2025-05-05 11:26:59 -0400)
>>>
>>> are available in the Git repository at:
>>>
>>>    https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull- 
>>> target-arm-20250506
>>>
>>> for you to fetch changes up to 607e1208b53ac713a76d158f4abc4cd2e8870051:
>>>
>>>    hw/arm/virt: Remove deprecated virt-4.0 machine (2025-05-06 
>>> 15:02:35 +0100)
>>>
>>> ----------------------------------------------------------------
>>> target-arm queue:
>>>   * hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX 
>>> SoC
>>>   * arm/hvf: fix crashes when using gdbstub
>>>   * target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug
>>>   * hw/arm/virt: Remove deprecated old versions of 'virt' machine
>>>   * tests/functional: Add test for imx8mp-evk board with USDHC coverage
>>>   * hw/arm: Attach PSPI module to NPCM8XX SoC
>>>   * target/arm: Don't assert() for ISB/SB inside IT block
>>>   * docs: Don't define duplicate label in qemu-block-drivers.rst.inc
>>>   * target/arm/kvm: Drop support for kernels without 
>>> KVM_ARM_PREFERRED_TARGET
>>>   * hw/pci-host/designware: Fix viewport configuration
>>>   * hw/gpio/imx_gpio: Fix interpretation of GDIR polarity
>>>
>>> ----------------------------------------------------------------
>>> Bernhard Beschow (4):
>>>        tests/functional: Add test for imx8mp-evk board with USDHC 
>>> coverage
>>>        hw/pci-host/designware: Remove unused include
>>>        hw/pci-host/designware: Fix viewport configuration
>>>        hw/gpio/imx_gpio: Fix interpretation of GDIR polarity
>>>
>>> Mads Ynddal (2):
>>>        hvf: avoid repeatedly setting trap debug for each cpu
>>>        hvf: only update sysreg from owning thread
>>
>> Please take a look at the following aarch64 macOS CI failure:
>>
>> ../accel/hvf/hvf-all.c:61:54: error: unknown type name 'run_on_cpu_data'
>> 61 | static void do_hvf_update_guest_debug(CPUState *cpu, 
>> run_on_cpu_data arg)
>> | ^
>> ../accel/hvf/hvf-all.c:68:5: error: call to undeclared function
>> 'run_on_cpu'; ISO C99 and later do not support implicit function
>> declarations [-Wimplicit-function-declaration]
>> 68 | run_on_cpu(cpu, do_hvf_update_guest_debug, RUN_ON_CPU_NULL);
>> | ^
>> ../accel/hvf/hvf-all.c:68:48: error: use of undeclared identifier
>> 'RUN_ON_CPU_NULL'
>> 68 | run_on_cpu(cpu, do_hvf_update_guest_debug, RUN_ON_CPU_NULL);
>> | ^
>> 3 errors generated.
>>
>> https://gitlab.com/qemu-project/qemu/-/jobs/9962088576
> 
> "hvf: only update sysreg from owning thread" missing:
> 
> -- >8 --
> diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c
> index 3fc65d6b231..8c387fda24d 100644
> --- a/accel/hvf/hvf-all.c
> +++ b/accel/hvf/hvf-all.c
> @@ -12,6 +12,7 @@
>   #include "qemu/error-report.h"
>   #include "system/hvf.h"
>   #include "system/hvf_int.h"
> +#include "hw/core/cpu.h"
> 
>   const char *hvf_return_string(hv_return_t ret)
>   {
> ---

Note, this is likely exposed (side effect) by:
https://lore.kernel.org/qemu-devel/20250506143512.4315-7-philmd@linaro.org/

Re: [PULL 00/32] target-arm queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 116 bytes --]

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[PULL 00/32] target-arm queue

[Peter Maydell]

Hi; here's the first target-arm pull for 10.2. Other than
Arm stuff I have included my update of kernel-doc to the new
upstream Python implementation.

thanks
-- PMM

The following changes since commit ca18b336e12c8433177a3cd639c5bf757952adaa:

  Merge tag 'pull-lu-20250828' of https://gitlab.com/rth7680/qemu into staging (2025-08-28 09:24:36 +1000)

are available in the Git repository at:

  https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250828

for you to fetch changes up to fd0b04e944df2e308a95ce9933ca4c04b3875a11:

  hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects (2025-08-28 10:26:25 +0100)

----------------------------------------------------------------
target-arm queue:
 * Implement FEAT_SCTLR2
 * Implement FEAT_TCR2
 * Implement FEAT_CSSC
 * Implement FEAT_LSE128
 * Clean up of register field definitions
 * Trap PMCR when MDCR_EL2.TPMCR is set
 * tests/functional: update aarch64 RME test images
 * hw/intc/arm_gicv3_kvm: preserve pending interrupts during cpr
 * hw/arm: add static NVDIMMs in device tree
 * hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects
 * scripts/kernel-doc: Avoid new Perl precedence warning
 * scripts/kernel-doc: Update to kernel's new Python implementation

----------------------------------------------------------------
Gustavo Romero (3):
      target/arm: Clean up of register field definitions
      target/arm: Implement FEAT_SCTLR2 and enable with -cpu max
      target/arm: Implement FEAT_TCR2 and enable with -cpu max

Manos Pitsidianakis (1):
      hw/arm: add static NVDIMMs in device tree

Peter Maydell (12):
      target/arm: Implement CTZ, CNT, ABS
      scripts/kernel-doc: Avoid new Perl precedence warning
      docs/sphinx/kerneldoc.py: Handle new LINENO syntax
      tests/qtest/libqtest.h: Remove stray space from doc comment
      scripts: Import Python kerneldoc from Linux kernel
      scripts/kernel-doc: strip QEMU_ from function definitions
      scripts/kernel-doc: tweak for QEMU coding standards
      scripts/kerneldoc: Switch to the Python kernel-doc script
      scripts/kernel-doc: Delete the old Perl kernel-doc script
      MAINTAINERS: Put kernel-doc under the "docs build machinery" section
      target/arm: Correct condition of aa64_atomics feature function
      hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects

Pierrick Bouvier (2):
      tests/functional/test_aarch64_device_passthrough: update image
      tests/functional/test_aarch64_rme: update image

Richard Henderson (12):
      target/arm: Add feature predicate for FEAT_CSSC
      target/arm: Implement MIN/MAX (immediate)
      target/arm: Implement MIN/MAX (register)
      target/arm: Split out gen_wrap2_i32 helper
      target/arm: Enable FEAT_CSSC for -cpu max
      qemu/atomic: Finish renaming atomic128-cas.h headers
      qemu/atomic: Add atomic16 primitives for xchg, fetch_and, fetch_or
      accel/tcg: Add cpu_atomic_*_mmu for 16-byte xchg, fetch_and, fetch_or
      tcg: Add tcg_gen_atomic_{xchg,fetch_and,fetch_or}_i128
      target/arm: Rename isar_feature_aa64_atomics
      target/arm: Implement FEAT_LSE128
      target/arm: Enable FEAT_LSE128 for -cpu max

Smail AIDER (1):
      target/arm: Trap PMCR when MDCR_EL2.TPMCR is set

Steve Sistare (1):
      hw/intc/arm_gicv3_kvm: preserve pending interrupts during cpr

 MAINTAINERS                                        |    3 +
 docs/conf.py                                       |    4 +-
 docs/sphinx/kerneldoc.py                           |    7 +-
 docs/system/arm/emulation.rst                      |    4 +
 accel/tcg/atomic_template.h                        |   80 +-
 accel/tcg/tcg-runtime.h                            |   12 +
 host/include/aarch64/host/atomic128-cas.h          |   45 -
 include/accel/tcg/cpu-ldst-common.h                |   13 +-
 include/hw/arm/stm32f205_soc.h                     |    2 +-
 include/hw/intc/arm_gicv3_common.h                 |    3 +
 include/tcg/tcg-op-common.h                        |    7 +
 include/tcg/tcg-op.h                               |    3 +
 target/arm/cpu-features.h                          |   24 +-
 target/arm/cpu.h                                   |   17 +
 target/arm/internals.h                             |   28 +-
 tests/qtest/libqtest.h                             |    2 +-
 host/include/aarch64/host/atomic128-cas.h.inc      |  102 +
 host/include/generic/host/atomic128-cas.h.inc      |   96 +
 target/arm/tcg/a64.decode                          |   26 +
 hw/arm/boot.c                                      |   42 +
 hw/arm/stm32f205_soc.c                             |   10 +-
 hw/arm/virt.c                                      |    8 +-
 hw/intc/arm_gicv3_kvm.c                            |   15 +
 linux-user/aarch64/elfload.c                       |    4 +-
 target/arm/cpregs-pmu.c                            |   34 +-
 target/arm/cpu.c                                   |    6 +
 target/arm/helper.c                                |  168 +-
 target/arm/ptw.c                                   |    8 +-
 target/arm/tcg/cpu64.c                             |    9 +-
 target/arm/tcg/translate-a64.c                     |  195 +-
 tcg/tcg-op-ldst.c                                  |   97 +-
 accel/tcg/atomic_common.c.inc                      |    9 +
 .editorconfig                                      |    2 +-
 scripts/kernel-doc                                 | 2442 --------------------
 scripts/kernel-doc.py                              |  325 +++
 scripts/lib/kdoc/kdoc_files.py                     |  291 +++
 scripts/lib/kdoc/kdoc_item.py                      |   42 +
 scripts/lib/kdoc/kdoc_output.py                    |  749 ++++++
 scripts/lib/kdoc/kdoc_parser.py                    | 1670 +++++++++++++
 scripts/lib/kdoc/kdoc_re.py                        |  270 +++
 .../functional/aarch64/test_device_passthrough.py  |   27 +-
 tests/functional/aarch64/test_rme_sbsaref.py       |   64 +-
 tests/functional/aarch64/test_rme_virt.py          |   85 +-
 43 files changed, 4388 insertions(+), 2662 deletions(-)
 delete mode 100644 host/include/aarch64/host/atomic128-cas.h
 create mode 100644 host/include/aarch64/host/atomic128-cas.h.inc
 delete mode 100755 scripts/kernel-doc
 create mode 100755 scripts/kernel-doc.py
 create mode 100644 scripts/lib/kdoc/kdoc_files.py
 create mode 100644 scripts/lib/kdoc/kdoc_item.py
 create mode 100644 scripts/lib/kdoc/kdoc_output.py
 create mode 100644 scripts/lib/kdoc/kdoc_parser.py
 create mode 100644 scripts/lib/kdoc/kdoc_re.py

[PULL 00/32] target-arm queue

[Peter Maydell]

target-arm queue: the big stuff here is the final part of
rth's patches for Cortex-A76 and Neoverse-N1 support;
also present are Gavin's NUMA series and a few other things.

thanks
-- PMM

The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:

  Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509

for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:

  hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)

----------------------------------------------------------------
target-arm queue:
 * MAINTAINERS/.mailmap: update email for Leif Lindholm
 * hw/arm: add version information to sbsa-ref machine DT
 * Enable new features for -cpu max:
   FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
   FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
 * Emulate Cortex-A76
 * Emulate Neoverse-N1
 * Fix the virt board default NUMA topology

----------------------------------------------------------------
Gavin Shan (6):
      qapi/machine.json: Add cluster-id
      qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
      hw/arm/virt: Consider SMP configuration in CPU topology
      qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
      hw/arm/virt: Fix CPU's default NUMA node ID
      hw/acpi/aml-build: Use existing CPU topology to build PPTT table

Leif Lindholm (2):
      MAINTAINERS/.mailmap: update email for Leif Lindholm
      hw/arm: add versioning to sbsa-ref machine DT

Richard Henderson (24):
      target/arm: Handle cpreg registration for missing EL
      target/arm: Drop EL3 no EL2 fallbacks
      target/arm: Merge zcr reginfo
      target/arm: Adjust definition of CONTEXTIDR_EL2
      target/arm: Move cortex impdef sysregs to cpu_tcg.c
      target/arm: Update qemu-system-arm -cpu max to cortex-a57
      target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
      target/arm: Split out aa32_max_features
      target/arm: Annotate arm_max_initfn with FEAT identifiers
      target/arm: Use field names for manipulating EL2 and EL3 modes
      target/arm: Enable FEAT_Debugv8p2 for -cpu max
      target/arm: Enable FEAT_Debugv8p4 for -cpu max
      target/arm: Add minimal RAS registers
      target/arm: Enable SCR and HCR bits for RAS
      target/arm: Implement virtual SError exceptions
      target/arm: Implement ESB instruction
      target/arm: Enable FEAT_RAS for -cpu max
      target/arm: Enable FEAT_IESB for -cpu max
      target/arm: Enable FEAT_CSV2 for -cpu max
      target/arm: Enable FEAT_CSV2_2 for -cpu max
      target/arm: Enable FEAT_CSV3 for -cpu max
      target/arm: Enable FEAT_DGH for -cpu max
      target/arm: Define cortex-a76
      target/arm: Define neoverse-n1

 docs/system/arm/emulation.rst |  10 +
 docs/system/arm/virt.rst      |   2 +
 qapi/machine.json             |   6 +-
 target/arm/cpregs.h           |  11 +
 target/arm/cpu.h              |  23 ++
 target/arm/helper.h           |   1 +
 target/arm/internals.h        |  16 ++
 target/arm/syndrome.h         |   5 +
 target/arm/a32.decode         |  16 +-
 target/arm/t32.decode         |  18 +-
 hw/acpi/aml-build.c           | 111 ++++----
 hw/arm/sbsa-ref.c             |  16 ++
 hw/arm/virt.c                 |  21 +-
 hw/core/machine-hmp-cmds.c    |   4 +
 hw/core/machine.c             |  16 ++
 target/arm/cpu.c              |  66 ++++-
 target/arm/cpu64.c            | 353 ++++++++++++++-----------
 target/arm/cpu_tcg.c          | 227 +++++++++++-----
 target/arm/helper.c           | 600 +++++++++++++++++++++++++-----------------
 target/arm/op_helper.c        |  43 +++
 target/arm/translate-a64.c    |  18 ++
 target/arm/translate.c        |  23 ++
 tests/qtest/numa-test.c       |  19 +-
 .mailmap                      |   3 +-
 MAINTAINERS                   |   2 +-
 25 files changed, 1068 insertions(+), 562 deletions(-)

Re: [PULL 00/32] target-arm queue

[Richard Henderson]

On 5/9/22 06:58, Peter Maydell wrote:
> target-arm queue: the big stuff here is the final part of
> rth's patches for Cortex-A76 and Neoverse-N1 support;
> also present are Gavin's NUMA series and a few other things.
> 
> thanks
> -- PMM
> 
> The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
> 
>    Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
> 
> are available in the Git repository at:
> 
>    https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
> 
> for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
> 
>    hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
> 
> ----------------------------------------------------------------
> target-arm queue:
>   * MAINTAINERS/.mailmap: update email for Leif Lindholm
>   * hw/arm: add version information to sbsa-ref machine DT
>   * Enable new features for -cpu max:
>     FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
>     FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
>   * Emulate Cortex-A76
>   * Emulate Neoverse-N1
>   * Fix the virt board default NUMA topology

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.


r~


> 
> ----------------------------------------------------------------
> Gavin Shan (6):
>        qapi/machine.json: Add cluster-id
>        qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
>        hw/arm/virt: Consider SMP configuration in CPU topology
>        qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
>        hw/arm/virt: Fix CPU's default NUMA node ID
>        hw/acpi/aml-build: Use existing CPU topology to build PPTT table
> 
> Leif Lindholm (2):
>        MAINTAINERS/.mailmap: update email for Leif Lindholm
>        hw/arm: add versioning to sbsa-ref machine DT
> 
> Richard Henderson (24):
>        target/arm: Handle cpreg registration for missing EL
>        target/arm: Drop EL3 no EL2 fallbacks
>        target/arm: Merge zcr reginfo
>        target/arm: Adjust definition of CONTEXTIDR_EL2
>        target/arm: Move cortex impdef sysregs to cpu_tcg.c
>        target/arm: Update qemu-system-arm -cpu max to cortex-a57
>        target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
>        target/arm: Split out aa32_max_features
>        target/arm: Annotate arm_max_initfn with FEAT identifiers
>        target/arm: Use field names for manipulating EL2 and EL3 modes
>        target/arm: Enable FEAT_Debugv8p2 for -cpu max
>        target/arm: Enable FEAT_Debugv8p4 for -cpu max
>        target/arm: Add minimal RAS registers
>        target/arm: Enable SCR and HCR bits for RAS
>        target/arm: Implement virtual SError exceptions
>        target/arm: Implement ESB instruction
>        target/arm: Enable FEAT_RAS for -cpu max
>        target/arm: Enable FEAT_IESB for -cpu max
>        target/arm: Enable FEAT_CSV2 for -cpu max
>        target/arm: Enable FEAT_CSV2_2 for -cpu max
>        target/arm: Enable FEAT_CSV3 for -cpu max
>        target/arm: Enable FEAT_DGH for -cpu max
>        target/arm: Define cortex-a76
>        target/arm: Define neoverse-n1
> 
>   docs/system/arm/emulation.rst |  10 +
>   docs/system/arm/virt.rst      |   2 +
>   qapi/machine.json             |   6 +-
>   target/arm/cpregs.h           |  11 +
>   target/arm/cpu.h              |  23 ++
>   target/arm/helper.h           |   1 +
>   target/arm/internals.h        |  16 ++
>   target/arm/syndrome.h         |   5 +
>   target/arm/a32.decode         |  16 +-
>   target/arm/t32.decode         |  18 +-
>   hw/acpi/aml-build.c           | 111 ++++----
>   hw/arm/sbsa-ref.c             |  16 ++
>   hw/arm/virt.c                 |  21 +-
>   hw/core/machine-hmp-cmds.c    |   4 +
>   hw/core/machine.c             |  16 ++
>   target/arm/cpu.c              |  66 ++++-
>   target/arm/cpu64.c            | 353 ++++++++++++++-----------
>   target/arm/cpu_tcg.c          | 227 +++++++++++-----
>   target/arm/helper.c           | 600 +++++++++++++++++++++++++-----------------
>   target/arm/op_helper.c        |  43 +++
>   target/arm/translate-a64.c    |  18 ++
>   target/arm/translate.c        |  23 ++
>   tests/qtest/numa-test.c       |  19 +-
>   .mailmap                      |   3 +-
>   MAINTAINERS                   |   2 +-
>   25 files changed, 1068 insertions(+), 562 deletions(-)
> 

[PULL 00/32] target-arm queue

[Peter Maydell]

The following changes since commit b367db48126d4ee14579af6cf5cdbffeb9496627:

  Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20220127' into staging (2022-01-28 11:05:29 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220128

for you to fetch changes up to 2c023d3675a3ffb54fc30504dcd715bc6f6e234f:

  target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp (2022-01-28 14:30:36 +0000)

----------------------------------------------------------------
target-arm queue:
 * Update copyright dates to 2022
 * hw/armv7m: Fix broken VMStateDescription
 * hw/char/exynos4210_uart: Fix crash on trying to load VM state
 * rtc: Move RTC function prototypes to their own header
 * xlnx-versal-virt: Support PMC SLCR
 * xlnx-versal-virt: Support OSPI flash memory controller
 * scripts: Explain the difference between linux-headers and standard-headers
 * target/arm: Log CPU index in 'Taking exception' log
 * arm_gicv3_its: Various bugfixes and cleanups
 * arm_gicv3_its: Implement the missing MOVI and MOVALL commands
 * ast2600: Fix address mapping of second SPI controller
 * target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp

----------------------------------------------------------------
Andrew Baumann (1):
      MAINTAINERS: Remove myself (for raspi).

Cédric Le Goater (1):
      hw/arm: ast2600: Fix address mapping of second SPI controller

Francisco Iglesias (10):
      hw/misc: Add a model of Versal's PMC SLCR
      hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models
      hw/arm/xlnx-versal: Connect Versal's PMC SLCR
      include/hw/dma/xlnx_csu_dma: Add in missing includes in the header
      hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method
      hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller
      hw/arm/xlnx-versal: Connect the OSPI flash memory controller model
      hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g
      hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI
      MAINTAINERS: Add an entry for Xilinx Versal OSPI

Peter Maydell (20):
      Update copyright dates to 2022
      hw/armv7m: Fix broken VMStateDescription
      hw/char/exynos4210_uart: Fix crash on trying to load VM state
      rtc: Move RTC function prototypes to their own header
      scripts: Explain the difference between linux-headers and standard-headers
      target/arm: Log CPU index in 'Taking exception' log
      hw/intc/arm_gicv3_its: Add tracepoints
      hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS
      hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set
      hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER
      hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs
      hw/intc/arm_gicv3_its: Sort ITS command list into numeric order
      hw/intc/arm_gicv3_redist: Remove unnecessary zero checks
      hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported
      hw/intc/arm_gicv3_its: Provide read accessor for translation_ops
      hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registers
      hw/intc/arm_gicv3_its: Check table bounds against correct limit
      hw/intc/arm_gicv3_its: Implement MOVALL
      hw/intc/arm_gicv3_its: Implement MOVI
      target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp

 docs/conf.py                               |    2 +-
 hw/intc/gicv3_internal.h                   |   43 +-
 include/hw/arm/xlnx-versal.h               |   30 +-
 include/hw/dma/xlnx_csu_dma.h              |   24 +-
 include/hw/intc/arm_gicv3_its_common.h     |    1 -
 include/hw/misc/xlnx-versal-pmc-iou-slcr.h |   78 ++
 include/hw/ssi/xlnx-versal-ospi.h          |  111 ++
 include/qemu-common.h                      |    5 +-
 include/sysemu/rtc.h                       |   58 +
 target/arm/internals.h                     |    2 +-
 hw/arm/armv7m.c                            |    4 +-
 hw/arm/aspeed_ast2600.c                    |    2 +-
 hw/arm/omap1.c                             |    2 +-
 hw/arm/pxa2xx.c                            |    2 +-
 hw/arm/strongarm.c                         |    2 +-
 hw/arm/xlnx-versal-virt.c                  |   25 +-
 hw/arm/xlnx-versal.c                       |  190 ++-
 hw/block/m25p80.c                          |    2 +
 hw/char/exynos4210_uart.c                  |    2 +-
 hw/dma/xlnx_csu_dma.c                      |   17 +
 hw/intc/arm_gicv3.c                        |    1 +
 hw/intc/arm_gicv3_common.c                 |    9 +
 hw/intc/arm_gicv3_its.c                    |  258 +++-
 hw/intc/arm_gicv3_redist.c                 |  115 +-
 hw/misc/mac_via.c                          |    2 +-
 hw/misc/macio/cuda.c                       |    2 +-
 hw/misc/macio/pmu.c                        |    2 +-
 hw/misc/xlnx-versal-pmc-iou-slcr.c         | 1446 ++++++++++++++++++++++
 hw/ppc/spapr_rtc.c                         |    2 +-
 hw/rtc/allwinner-rtc.c                     |    2 +-
 hw/rtc/aspeed_rtc.c                        |    2 +-
 hw/rtc/ds1338.c                            |    2 +-
 hw/rtc/exynos4210_rtc.c                    |    2 +-
 hw/rtc/goldfish_rtc.c                      |    2 +-
 hw/rtc/m41t80.c                            |    2 +-
 hw/rtc/m48t59.c                            |    2 +-
 hw/rtc/mc146818rtc.c                       |    2 +-
 hw/rtc/pl031.c                             |    2 +-
 hw/rtc/twl92230.c                          |    2 +-
 hw/rtc/xlnx-zynqmp-rtc.c                   |    2 +-
 hw/s390x/tod-tcg.c                         |    2 +-
 hw/scsi/megasas.c                          |    2 +-
 hw/ssi/xlnx-versal-ospi.c                  | 1853 ++++++++++++++++++++++++++++
 net/dump.c                                 |    2 +-
 softmmu/rtc.c                              |    2 +-
 target/arm/helper.c                        |   13 +-
 target/arm/m_helper.c                      |    2 +-
 MAINTAINERS                                |    7 +-
 hw/intc/trace-events                       |    8 +
 hw/misc/meson.build                        |    5 +-
 hw/ssi/meson.build                         |    1 +
 scripts/update-linux-headers.sh            |   16 +
 52 files changed, 4300 insertions(+), 74 deletions(-)
 create mode 100644 include/hw/misc/xlnx-versal-pmc-iou-slcr.h
 create mode 100644 include/hw/ssi/xlnx-versal-ospi.h
 create mode 100644 include/sysemu/rtc.h
 create mode 100644 hw/misc/xlnx-versal-pmc-iou-slcr.c
 create mode 100644 hw/ssi/xlnx-versal-ospi.c

Re: [PULL 00/32] target-arm queue

[Peter Maydell]

On Fri, 28 Jan 2022 at 15:30, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit b367db48126d4ee14579af6cf5cdbffeb9496627:
>
>   Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20220127' into staging (2022-01-28 11:05:29 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220128
>
> for you to fetch changes up to 2c023d3675a3ffb54fc30504dcd715bc6f6e234f:
>
>   target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp (2022-01-28 14:30:36 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Update copyright dates to 2022
>  * hw/armv7m: Fix broken VMStateDescription
>  * hw/char/exynos4210_uart: Fix crash on trying to load VM state
>  * rtc: Move RTC function prototypes to their own header
>  * xlnx-versal-virt: Support PMC SLCR
>  * xlnx-versal-virt: Support OSPI flash memory controller
>  * scripts: Explain the difference between linux-headers and standard-headers
>  * target/arm: Log CPU index in 'Taking exception' log
>  * arm_gicv3_its: Various bugfixes and cleanups
>  * arm_gicv3_its: Implement the missing MOVI and MOVALL commands
>  * ast2600: Fix address mapping of second SPI controller
>  * target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.

-- PMM