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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e1522a667sm111765955ad.171.2025.05.08.06.39.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 08 May 2025 06:39:24 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Sergio Lopez , Gerd Hoffmann , Peter Maydell , Laurent Vivier , Jiaxun Yang , Yi Liu , "Michael S. Tsirkin" , Eduardo Habkost , Marcel Apfelbaum , Alistair Francis , Daniel Henrique Barboza , Marcelo Tosatti , qemu-riscv@nongnu.org, Weiwei Li , Amit Shah , Zhao Liu , Yanan Wang , Helge Deller , Palmer Dabbelt , Ani Sinha , Igor Mammedov , Fabiano Rosas , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Liu Zhiwei , =?UTF-8?q?Cl=C3=A9ment=20Mathieu--Drif?= , qemu-arm@nongnu.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Huacai Chen , Jason Wang Subject: [PATCH v4 09/27] hw/nvram/fw_cfg: Remove fw_cfg_io_properties::dma_enabled Date: Thu, 8 May 2025 15:35:32 +0200 Message-ID: <20250508133550.81391-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250508133550.81391-1-philmd@linaro.org> References: <20250508133550.81391-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=philmd@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now than all calls to fw_cfg_init_io_dma() pass DMA arguments, the 'dma_enabled' of the TYPE_FW_CFG_IO type is not used anymore. Remove it, simplifying fw_cfg_init_io_dma() and fw_cfg_io_realize(). Note, we can not remove the equivalent in fw_cfg_mem_properties[] because it is still used in HPPA and MIPS Loongson3 machines: $ git grep -w fw_cfg_init_mem_nodma hw/hppa/machine.c:204: fw_cfg = fw_cfg_init_mem_nodma(addr, addr + 4, 1); hw/mips/loongson3_virt.c:289: fw_cfg = fw_cfg_init_mem_nodma(cfg_addr, cfg_addr + 8, 8); 'linuxboot.bin' isn't used anymore, we'll remove it in the next commit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu --- hw/i386/fw_cfg.c | 5 +---- hw/i386/x86-common.c | 5 +---- hw/nvram/fw_cfg.c | 26 ++++++++------------------ 3 files changed, 10 insertions(+), 26 deletions(-) diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index 5c0bcd5f8a9..1fe084fd720 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -221,10 +221,7 @@ void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ - Object *obj = OBJECT(fw_cfg); - uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ? - ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : - FW_CFG_CTL_SIZE; + uint8_t io_size = ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t); Aml *dev = aml_device("FWCF"); Aml *crs = aml_resource_template(); diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 27254a0e9f1..ee594364415 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -991,10 +991,7 @@ void x86_load_linux(X86MachineState *x86ms, } option_rom[nb_option_roms].bootindex = 0; - option_rom[nb_option_roms].name = "linuxboot.bin"; - if (fw_cfg_dma_enabled(fw_cfg)) { - option_rom[nb_option_roms].name = "linuxboot_dma.bin"; - } + option_rom[nb_option_roms].name = "linuxboot_dma.bin"; nb_option_roms++; } diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 51b028b5d0a..ef976a4bce2 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1026,12 +1026,9 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, FWCfgIoState *ios; FWCfgState *s; MemoryRegion *iomem = get_system_io(); - bool dma_requested = dma_iobase && dma_as; + assert(dma_iobase); dev = qdev_new(TYPE_FW_CFG_IO); - if (!dma_requested) { - qdev_prop_set_bit(dev, "dma_enabled", false); - } object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, OBJECT(dev)); @@ -1042,13 +1039,10 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, memory_region_add_subregion(iomem, iobase, &ios->comb_iomem); s = FW_CFG(dev); - - if (s->dma_enabled) { - /* 64 bits for the address field */ - s->dma_as = dma_as; - s->dma_addr = 0; - memory_region_add_subregion(iomem, dma_iobase, &s->dma_iomem); - } + /* 64 bits for the address field */ + s->dma_as = dma_as; + s->dma_addr = 0; + memory_region_add_subregion(iomem, dma_iobase, &s->dma_iomem); return s; } @@ -1185,8 +1179,6 @@ static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp) } static const Property fw_cfg_io_properties[] = { - DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled, - true), DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots, FW_CFG_FILE_SLOTS_DFLT), }; @@ -1207,11 +1199,9 @@ static void fw_cfg_io_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops, FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE); - if (FW_CFG(s)->dma_enabled) { - memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), - &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", - sizeof(dma_addr_t)); - } + memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), + &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", + sizeof(dma_addr_t)); fw_cfg_common_realize(dev, errp); } -- 2.47.1