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Sun, 11 May 2025 20:13:14 -0700 (PDT) Received: from wheely.local0.net ([118.209.229.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b234951024csm4750069a12.5.2025.05.11.20.13.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 May 2025 20:13:13 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Glenn Miles , Michael Kowal , Caleb Schlossin Subject: [PATCH 34/50] ppc/xive: tctx_accept only lower irq line if an interrupt was presented Date: Mon, 12 May 2025 13:10:43 +1000 Message-ID: <20250512031100.439842-35-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250512031100.439842-1-npiggin@gmail.com> References: <20250512031100.439842-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=npiggin@gmail.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The relationship between an interrupt signaled in the TIMA and the QEMU irq line to the processor to be 1:1, so they should be raised and lowered together and "just in case" lowering should be avoided (it could mask Signed-off-by: Nicholas Piggin --- hw/intc/xive.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 4e0c71d684..d5dbeab6bd 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -95,8 +95,6 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring) g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); - qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); - if (xive_nsr_indicates_exception(sig_ring, nsr)) { uint8_t cppr = sig_regs[TM_PIPR]; uint8_t ring; @@ -117,6 +115,7 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring) /* Clear the exception from NSR */ sig_regs[TM_NSR] = 0; + qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); trace_xive_tctx_accept(tctx->cs->cpu_index, ring, regs[TM_IPB], sig_regs[TM_PIPR], -- 2.47.1