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Sun, 11 May 2025 20:13:21 -0700 (PDT) Received: from wheely.local0.net ([118.209.229.237]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b234951024csm4750069a12.5.2025.05.11.20.13.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 May 2025 20:13:21 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , Glenn Miles , Michael Kowal , Caleb Schlossin Subject: [PATCH 36/50] ppc/xive2: split tctx presentation processing from set CPPR Date: Mon, 12 May 2025 13:10:45 +1000 Message-ID: <20250512031100.439842-37-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250512031100.439842-1-npiggin@gmail.com> References: <20250512031100.439842-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The second part of the set CPPR operation is to process (or re-present) any pending interrupts after CPPR is adjusted. Split this presentation processing out into a standalone function that can be used in other places. Signed-off-by: Nicholas Piggin --- hw/intc/xive2.c | 137 +++++++++++++++++++++++++++--------------------- 1 file changed, 76 insertions(+), 61 deletions(-) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 8c8dab3aa2..aa06bfda77 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1098,66 +1098,19 @@ void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS); } -/* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ -static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) +/* Re-calculate and present pending interrupts */ +static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring) { - uint8_t *sig_regs = &tctx->regs[ring]; + uint8_t *sig_regs = &tctx->regs[sig_ring]; Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr); - uint8_t old_cppr, backlog_prio, first_group, group_level; + uint8_t backlog_prio, first_group, group_level; uint8_t pipr_min, lsmfb_min, ring_min; + uint8_t cppr = sig_regs[TM_CPPR]; bool group_enabled; - uint8_t nvp_blk; - uint32_t nvp_idx; Xive2Nvp nvp; int rc; - uint8_t nsr = sig_regs[TM_NSR]; - - g_assert(ring == TM_QW1_OS || ring == TM_QW3_HV_PHYS); - - g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0); - g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); - g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); - - /* XXX: should show pool IPB for PHYS ring */ - trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, - sig_regs[TM_IPB], sig_regs[TM_PIPR], - cppr, nsr); - - if (cppr > XIVE_PRIORITY_MAX) { - cppr = 0xff; - } - - old_cppr = sig_regs[TM_CPPR]; - sig_regs[TM_CPPR] = cppr; - - /* Handle increased CPPR priority (lower value) */ - if (cppr < old_cppr) { - if (cppr <= sig_regs[TM_PIPR]) { - /* CPPR lowered below PIPR, must un-present interrupt */ - if (xive_nsr_indicates_exception(ring, nsr)) { - if (xive_nsr_indicates_group_exception(ring, nsr)) { - /* redistribute precluded active grp interrupt */ - xive2_redistribute(xrtr, tctx, - xive_nsr_exception_ring(ring, nsr)); - return; - } - } - /* interrupt is VP directed, pending in IPB */ - xive_tctx_pipr_set(tctx, ring, cppr, 0); - return; - } else { - /* CPPR was lowered, but still above PIPR. No action needed. */ - return; - } - } - - /* CPPR didn't change, nothing needs to be done */ - if (cppr == old_cppr) { - return; - } - - /* CPPR priority decreased (higher value) */ + g_assert(sig_ring == TM_QW3_HV_PHYS || sig_ring == TM_QW1_OS); /* * Recompute the PIPR based on local pending interrupts. It will @@ -1167,11 +1120,11 @@ again: pipr_min = xive_ipb_to_pipr(sig_regs[TM_IPB]); group_enabled = !!sig_regs[TM_LGS]; lsmfb_min = group_enabled ? sig_regs[TM_LSMFB] : 0xff; - ring_min = ring; + ring_min = sig_ring; group_level = 0; /* PHYS updates also depend on POOL values */ - if (ring == TM_QW3_HV_PHYS) { + if (sig_ring == TM_QW3_HV_PHYS) { uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; /* POOL values only matter if POOL ctx is valid */ @@ -1201,20 +1154,25 @@ again: } } - rc = xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx); - if (rc) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid context\n"); - return; - } - if (group_enabled && lsmfb_min < cppr && lsmfb_min < pipr_min) { + + uint8_t nvp_blk; + uint32_t nvp_idx; + /* * Thread has seen a group interrupt with a higher priority * than the new cppr or pending local interrupt. Check the * backlog */ + rc = xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx); + if (rc) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid " + "context\n"); + return; + } + if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", nvp_blk, nvp_idx); @@ -1260,6 +1218,63 @@ again: xive_tctx_pipr_set(tctx, ring_min, pipr_min, group_level); } +/* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ +static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t sig_ring, uint8_t cppr) +{ + uint8_t *sig_regs = &tctx->regs[sig_ring]; + Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr); + uint8_t old_cppr; + uint8_t nsr = sig_regs[TM_NSR]; + + g_assert(sig_ring == TM_QW1_OS || sig_ring == TM_QW3_HV_PHYS); + + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); + g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); + + /* XXX: should show pool IPB for PHYS ring */ + trace_xive_tctx_set_cppr(tctx->cs->cpu_index, sig_ring, + sig_regs[TM_IPB], sig_regs[TM_PIPR], + cppr, nsr); + + if (cppr > XIVE_PRIORITY_MAX) { + cppr = 0xff; + } + + old_cppr = sig_regs[TM_CPPR]; + sig_regs[TM_CPPR] = cppr; + + /* Handle increased CPPR priority (lower value) */ + if (cppr < old_cppr) { + if (cppr <= sig_regs[TM_PIPR]) { + /* CPPR lowered below PIPR, must un-present interrupt */ + if (xive_nsr_indicates_exception(sig_ring, nsr)) { + if (xive_nsr_indicates_group_exception(sig_ring, nsr)) { + /* redistribute precluded active grp interrupt */ + xive2_redistribute(xrtr, tctx, + xive_nsr_exception_ring(sig_ring, nsr)); + return; + } + } + + /* interrupt is VP directed, pending in IPB */ + xive_tctx_pipr_set(tctx, sig_ring, cppr, 0); + return; + } else { + /* CPPR was lowered, but still above PIPR. No action needed. */ + return; + } + } + + /* CPPR didn't change, nothing needs to be done */ + if (cppr == old_cppr) { + return; + } + + /* CPPR priority decreased (higher value) */ + xive2_tctx_process_pending(tctx, sig_ring); +} + void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size) { -- 2.47.1