From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: dbarboza@ventanamicro.com, alistair23@gmail.com,
richard.henderson@linaro.org
Subject: [PATCH 16/26] target/riscv: convert SiFive E CPU models to RISCVCPUDef
Date: Mon, 12 May 2025 11:52:16 +0200 [thread overview]
Message-ID: <20250512095226.93621-17-pbonzini@redhat.com> (raw)
In-Reply-To: <20250512095226.93621-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 74 ++++++++++++------------------------------
2 files changed, 21 insertions(+), 54 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 4cfdb74891e..0f9be15e47b 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -44,6 +44,7 @@
#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
+#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b4f6e34eac7..aea5d7d197e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -503,23 +503,6 @@ static void rv64_sifive_u_cpu_init(Object *obj)
cpu->cfg.pmp = true;
}
-static void rv64_sifive_e_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
-}
-
static void rv64_thead_c906_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -708,23 +691,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
cpu->cfg.pmp = true;
}
-static void rv32_sifive_e_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
-}
-
static void rv32_ibex_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -746,23 +712,6 @@ static void rv32_ibex_cpu_init(Object *obj)
cpu->cfg.ext_zbc = true;
cpu->cfg.ext_zbs = true;
}
-
-static void rv32_imafcu_nommu_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
-}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -3204,6 +3153,15 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
),
+ DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E, TYPE_RISCV_VENDOR_CPU,
+ .misa_ext = RVI | RVM | RVA | RVC | RVU,
+ .priv_spec = PRIV_VERSION_1_10_0,
+ .cfg.max_satp_mode = VM_1_10_MBARE,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ .cfg.pmp = true
+ ),
+
#if defined(TARGET_RISCV32) || \
(defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
@@ -3212,8 +3170,14 @@ static const TypeInfo riscv_cpu_type_infos[] = {
),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
+ .misa_mxl_max = MXL_RV32
+ ),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E34, TYPE_RISCV_CPU_SIFIVE_E,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVF, /* IMAFCU */
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
@@ -3239,7 +3203,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV64,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
+ .misa_mxl_max = MXL_RV64
+ ),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),
--
2.49.0
next prev parent reply other threads:[~2025-05-12 10:04 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-12 9:52 [PATCH v5 00/26] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-05-12 9:52 ` [PATCH 01/26] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-05-12 9:52 ` [PATCH 02/26] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-05-12 9:52 ` [PATCH 03/26] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-05-12 9:52 ` [PATCH 04/26] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-05-12 9:52 ` [PATCH 05/26] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-05-12 9:52 ` [PATCH 06/26] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-05-15 4:51 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 07/26] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-05-12 9:52 ` [PATCH 08/26] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-05-12 9:52 ` [PATCH 09/26] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-05-12 9:52 ` [PATCH 10/26] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-05-15 4:51 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 11/26] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-05-15 5:00 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 12/26] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-05-15 5:28 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 13/26] target/riscv: convert profile CPU models " Paolo Bonzini
2025-05-15 5:29 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 14/26] target/riscv: convert bare " Paolo Bonzini
2025-05-15 5:30 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 15/26] target/riscv: convert dynamic " Paolo Bonzini
2025-05-15 5:31 ` Alistair Francis
2025-05-12 9:52 ` Paolo Bonzini [this message]
2025-05-15 5:32 ` [PATCH 16/26] target/riscv: convert SiFive E " Alistair Francis
2025-05-12 9:52 ` [PATCH 17/26] target/riscv: convert ibex " Paolo Bonzini
2025-05-15 5:32 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 18/26] target/riscv: convert SiFive U " Paolo Bonzini
2025-05-15 5:34 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 19/26] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-05-15 5:38 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 20/26] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-05-15 5:40 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 21/26] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-05-15 5:41 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 22/26] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-05-15 5:42 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 23/26] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-05-15 5:43 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 24/26] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-05-15 5:44 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 25/26] target/riscv: remove .instance_post_init Paolo Bonzini
2025-05-12 10:33 ` Philippe Mathieu-Daudé
2025-05-12 10:39 ` Paolo Bonzini
2025-05-15 5:45 ` Alistair Francis
2025-05-12 9:52 ` [PATCH 26/26] qom: reverse order of instance_post_init calls Paolo Bonzini
2025-05-15 6:05 ` [PATCH v5 00/26] target/riscv: SATP mode and CPU definition overhaul Alistair Francis
2025-05-20 6:17 ` Paolo Bonzini
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