From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, Fan Ni <fan.ni@samsung.com>,
Peter Maydell <peter.maydell@linaro.org>, <mst@redhat.com>
Cc: linux-cxl@vger.kernel.org, linuxarm@huawei.com,
qemu-arm@nongnu.org,
"Yuquan Wang" <wangyuquan1236@phytium.com.cn>,
"Itaru Kitayama" <itaru.kitayama@linux.dev>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v13 3/5] hw/cxl-host: Allow split of establishing memory address and mmio setup.
Date: Tue, 13 May 2025 12:14:53 +0100 [thread overview]
Message-ID: <20250513111455.128266-4-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20250513111455.128266-1-Jonathan.Cameron@huawei.com>
On arm/virt the memory map is set up before any devices are brought
up. To enable this provide split functions to establish the fw->base
and later to actually map it.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
include/hw/cxl/cxl_host.h | 2 ++
hw/cxl/cxl-host-stubs.c | 2 ++
hw/cxl/cxl-host.c | 44 ++++++++++++++++++++++++++++++++++++++-
3 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h
index 6dce2cde07..aee9d573d6 100644
--- a/include/hw/cxl/cxl_host.h
+++ b/include/hw/cxl/cxl_host.h
@@ -16,6 +16,8 @@
void cxl_machine_init(Object *obj, CXLState *state);
void cxl_fmws_link_targets(Error **errp);
void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp);
+hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr);
+void cxl_fmws_update_mmio(void);
hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr);
GSList *cxl_fmws_get_all_sorted(void);
diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
index 13eb6bf6a4..d9e38618d6 100644
--- a/hw/cxl/cxl-host-stubs.c
+++ b/hw/cxl/cxl-host-stubs.c
@@ -11,6 +11,8 @@
void cxl_fmws_link_targets(Error **errp) {};
void cxl_machine_init(Object *obj, CXLState *state) {};
void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp) {};
+hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr) { return base; };
+void cxl_fmws_update_mmio(void) {};
hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr)
{
return base;
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index 438f2920e1..3b9184e7e7 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -383,6 +383,7 @@ void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
struct cfmw_update_state {
hwaddr base;
hwaddr maxaddr;
+ bool update_mmio;
};
static void cxl_fmws_update(Object *obj, void *opaque)
@@ -397,7 +398,9 @@ static void cxl_fmws_update(Object *obj, void *opaque)
fw = CXL_FMW(obj);
if (s->base + fw->size <= s->maxaddr) {
fw->base = s->base;
- sysbus_mmio_map(SYS_BUS_DEVICE(fw), 0, fw->base);
+ if (s->update_mmio) {
+ sysbus_mmio_map(SYS_BUS_DEVICE(fw), 0, fw->base);
+ }
s->base += fw->size;
}
@@ -438,6 +441,24 @@ GSList *cxl_fmws_get_all_sorted(void)
return g_slist_sort_with_data(cxl_fmws_get_all(), cfmws_cmp, NULL);
}
+hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr)
+{
+ GSList *cfmws_list, *iter;
+
+ struct cfmw_update_state cfmwss = {
+ .base = base,
+ .maxaddr = max_addr,
+ .update_mmio = false,
+ };
+ cfmws_list = cxl_fmws_get_all_sorted();
+ for (iter = cfmws_list; iter; iter = iter->next) {
+ cxl_fmws_update(iter->data, &cfmwss);
+ }
+ g_slist_free(cfmws_list);
+
+ return cfmwss.base;
+}
+
hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr)
{
GSList *cfmws_list, *iter;
@@ -445,6 +466,7 @@ hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr)
struct cfmw_update_state cfmwss = {
.base = base,
.maxaddr = max_addr,
+ .update_mmio = true,
};
cfmws_list = cxl_fmws_get_all_sorted();
for (iter = cfmws_list; iter; iter = iter->next) {
@@ -455,6 +477,26 @@ hwaddr cxl_fmws_set_memmap_and_update_mmio(hwaddr base, hwaddr max_addr)
return cfmwss.base;
}
+static int cxl_fmws_mmio_map(Object *obj, void *opaque)
+{
+ struct CXLFixedWindow *fw;
+
+ if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) {
+ return 0;
+ }
+ fw = CXL_FMW(obj);
+ sysbus_mmio_map(SYS_BUS_DEVICE(fw), 0, fw->base);
+
+ return 0;
+}
+
+void cxl_fmws_update_mmio(void)
+{
+ /* Ordering is not required for this */
+ object_child_foreach_recursive(object_get_root(), cxl_fmws_mmio_map,
+ NULL);
+}
+
static void cxl_fmw_realize(DeviceState *dev, Error **errp)
{
CXLFixedWindow *fw = CXL_FMW(dev);
--
2.43.0
next prev parent reply other threads:[~2025-05-13 11:16 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-13 11:14 [PATCH v13 0/5] arm/virt: CXL support via pxb_cxl Jonathan Cameron via
2025-05-13 11:14 ` [PATCH v13 1/5] hw/cxl-host: Add an index field to CXLFixedMemoryWindow Jonathan Cameron via
2025-05-16 5:44 ` Zhijian Li (Fujitsu) via
2025-05-21 16:59 ` Fan Ni
2025-08-08 8:29 ` wangyuquan
2025-08-08 8:44 ` Yuquan Wang
2025-05-13 11:14 ` [PATCH v13 2/5] hw/cxl: Make the CXL fixed memory windows devices Jonathan Cameron via
2025-05-16 5:44 ` Zhijian Li (Fujitsu) via
2025-05-21 17:54 ` Fan Ni
2025-05-27 16:04 ` Jonathan Cameron via
2025-05-13 11:14 ` Jonathan Cameron via [this message]
2025-05-16 5:50 ` [PATCH v13 3/5] hw/cxl-host: Allow split of establishing memory address and mmio setup Zhijian Li (Fujitsu) via
2025-05-27 16:28 ` Jonathan Cameron via
2025-05-13 11:14 ` [PATCH v13 4/5] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron via
2025-05-13 11:14 ` [PATCH v13 5/5] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron via
2025-05-15 9:04 ` Itaru Kitayama
2025-05-19 12:54 ` Jonathan Cameron via
2025-05-20 20:38 ` Itaru Kitayama
2025-05-21 7:38 ` Itaru Kitayama
2025-05-21 17:52 ` Jonathan Cameron via
2025-05-21 22:07 ` Itaru Kitayama
2025-05-16 2:30 ` [PATCH v13 0/5] arm/virt: CXL support via pxb_cxl Itaru Kitayama
2025-05-16 6:34 ` Itaru Kitayama
2025-05-20 17:31 ` Jonathan Cameron via
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