qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Igor Mammedov <imammedo@redhat.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	kvm@vger.kernel.org, "Sergio Lopez" <slp@redhat.com>,
	"Gerd Hoffmann" <kraxel@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Laurent Vivier" <lvivier@redhat.com>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Yi Liu" <yi.l.liu@intel.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Marcelo Tosatti" <mtosatti@redhat.com>,
	qemu-riscv@nongnu.org, "Weiwei Li" <liwei1518@gmail.com>,
	"Amit Shah" <amit@kernel.org>, "Zhao Liu" <zhao1.liu@intel.com>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	"Helge Deller" <deller@gmx.de>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Ani Sinha" <anisinha@redhat.com>,
	"Fabiano Rosas" <farosas@suse.de>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Clément Mathieu--Drif" <clement.mathieu--drif@eviden.com>,
	qemu-arm@nongnu.org,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Jason Wang" <jasowang@redhat.com>
Subject: Re: [PATCH v4 19/27] target/i386/cpu: Remove CPUX86State::full_cpuid_auto_level field
Date: Tue, 13 May 2025 13:02:24 +0200	[thread overview]
Message-ID: <20250513130224.3aa2e837@imammedo.users.ipa.redhat.com> (raw)
In-Reply-To: <20250508133550.81391-20-philmd@linaro.org>

On Thu,  8 May 2025 15:35:42 +0200
Philippe Mathieu-Daudé <philmd@linaro.org> wrote:

> The CPUX86State::full_cpuid_auto_level boolean was only
> disabled for the pc-q35-2.7 and pc-i440fx-2.7 machines,
> which got removed. Being now always %true, we can remove
> it and simplify x86_cpu_expand_features().

I've found field being mentioned only by some external rust library,
that's likely shouldn't concern QEMU qemu though.

I'm not confident enough to ack it but I won't object either
 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/i386/cpu.h |   3 --
>  target/i386/cpu.c | 106 ++++++++++++++++++++++------------------------
>  2 files changed, 51 insertions(+), 58 deletions(-)
> 
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 7585407da54..b5cbd91c156 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2241,9 +2241,6 @@ struct ArchCPU {
>       */
>      bool legacy_multi_node;
>  
> -    /* Enable auto level-increase for all CPUID leaves */
> -    bool full_cpuid_auto_level;
> -
>      /* Only advertise CPUID leaves defined by the vendor */
>      bool vendor_cpuid_only;
>  
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index fb505d13122..6b9a1f2251a 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -7843,68 +7843,65 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
>  
>      /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
>      x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
> -    if (cpu->full_cpuid_auto_level) {
> -        x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
> -        x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
> +    x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
>  
> -        /* Intel Processor Trace requires CPUID[0x14] */
> -        if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
> -            if (cpu->intel_pt_auto_level) {
> -                x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
> -            } else if (cpu->env.cpuid_min_level < 0x14) {
> -                mark_unavailable_features(cpu, FEAT_7_0_EBX,
> -                    CPUID_7_0_EBX_INTEL_PT,
> -                    "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
> -            }
> +    /* Intel Processor Trace requires CPUID[0x14] */
> +    if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
> +        if (cpu->intel_pt_auto_level) {
> +            x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
> +        } else if (cpu->env.cpuid_min_level < 0x14) {
> +            mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT,
> +                "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
>          }
> +    }
>  
> -        /*
> -         * Intel CPU topology with multi-dies support requires CPUID[0x1F].
> -         * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
> -         * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
> -         * cpu->vendor_cpuid_only has been unset for compatibility with older
> -         * machine types.
> -         */
> -        if (x86_has_extended_topo(env->avail_cpu_topo) &&
> -            (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
> -            x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
> -        }
> +    /*
> +     * Intel CPU topology with multi-dies support requires CPUID[0x1F].
> +     * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
> +     * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
> +     * cpu->vendor_cpuid_only has been unset for compatibility with older
> +     * machine types.
> +     */
> +    if (x86_has_extended_topo(env->avail_cpu_topo) &&
> +        (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
> +        x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
> +    }
>  
> -        /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */
> -        if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) {
> -            x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24);
> -        }
> +    /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */
> +    if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) {
> +        x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24);
> +    }
>  
> -        /* SVM requires CPUID[0x8000000A] */
> -        if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
> -            x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
> -        }
> +    /* SVM requires CPUID[0x8000000A] */
> +    if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
> +        x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
> +    }
>  
> -        /* SEV requires CPUID[0x8000001F] */
> -        if (sev_enabled()) {
> -            x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
> -        }
> +    /* SEV requires CPUID[0x8000001F] */
> +    if (sev_enabled()) {
> +        x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
> +    }
>  
> -        if (env->features[FEAT_8000_0021_EAX]) {
> -            x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021);
> -        }
> +    if (env->features[FEAT_8000_0021_EAX]) {
> +        x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021);
> +    }
>  
> -        /* SGX requires CPUID[0x12] for EPC enumeration */
> -        if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
> -            x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
> -        }
> +    /* SGX requires CPUID[0x12] for EPC enumeration */
> +    if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
> +        x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
>      }
>  
>      /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
> @@ -8820,7 +8817,6 @@ static const Property x86_cpu_properties[] = {
>      DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
>      DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0),
>      DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
> -    DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
>      DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
>      DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
>      DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true),



  parent reply	other threads:[~2025-05-13 11:03 UTC|newest]

Thread overview: 109+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-08 13:35 [PATCH v4 00/27] hw/i386/pc: Remove deprecated 2.6 and 2.7 PC machines Philippe Mathieu-Daudé
2025-05-08 13:35 ` [PATCH v4 01/27] hw/i386/pc: Remove deprecated pc-q35-2.6 and pc-i440fx-2.6 machines Philippe Mathieu-Daudé
2025-05-09 15:23   ` Igor Mammedov
2025-06-02  6:13     ` Thomas Huth
2025-06-02  8:53       ` Philippe Mathieu-Daudé
2025-06-02 10:26         ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 02/27] hw/i386/pc: Remove PCMachineClass::legacy_cpu_hotplug field Philippe Mathieu-Daudé
2025-05-09 15:18   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 03/27] hw/nvram/fw_cfg: Rename fw_cfg_init_mem() with '_nodma' suffix Philippe Mathieu-Daudé
2025-05-09  2:49   ` Zhao Liu
2025-05-09 15:33   ` Igor Mammedov
2025-05-15  8:04   ` Xiaoyao Li
2025-05-08 13:35 ` [PATCH v4 04/27] hw/mips/loongson3_virt: Prefer using fw_cfg_init_mem_nodma() Philippe Mathieu-Daudé
2025-05-09  2:49   ` Zhao Liu
2025-05-09 15:35   ` Igor Mammedov
2025-05-15  8:05   ` Xiaoyao Li
2025-05-08 13:35 ` [PATCH v4 05/27] hw/nvram/fw_cfg: Factor fw_cfg_init_mem_internal() out Philippe Mathieu-Daudé
2025-05-09  2:50   ` Zhao Liu
2025-05-09 15:38   ` Igor Mammedov
2025-05-15  8:08   ` Xiaoyao Li
2025-05-08 13:35 ` [PATCH v4 06/27] hw/nvram/fw_cfg: Rename fw_cfg_init_mem_wide() -> fw_cfg_init_mem_dma() Philippe Mathieu-Daudé
2025-05-09  2:52   ` Zhao Liu
2025-05-09  6:51   ` Zhao Liu
2025-05-09 15:39     ` Igor Mammedov
2025-05-15  8:17   ` Xiaoyao Li
2025-05-08 13:35 ` [PATCH v4 07/27] hw/i386/x86: Remove X86MachineClass::fwcfg_dma_enabled field Philippe Mathieu-Daudé
2025-05-09  3:23   ` Zhao Liu
2025-05-09 15:41   ` Igor Mammedov
2025-05-09 15:44     ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 08/27] hw/i386/pc: Remove multiboot.bin Philippe Mathieu-Daudé
2025-05-09  6:11   ` Zhao Liu
2025-05-08 13:35 ` [PATCH v4 09/27] hw/nvram/fw_cfg: Remove fw_cfg_io_properties::dma_enabled Philippe Mathieu-Daudé
2025-05-09  6:37   ` Zhao Liu
2025-05-09 16:00   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 10/27] hw/i386/pc: Remove linuxboot.bin Philippe Mathieu-Daudé
2025-05-09  6:53   ` Zhao Liu
2025-05-09 16:04   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 11/27] hw/i386/pc: Remove pc_compat_2_6[] array Philippe Mathieu-Daudé
2025-05-09  6:54   ` Zhao Liu
2025-05-12  8:19   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 12/27] target/i386/cpu: Remove CPUX86State::enable_cpuid_0xb field Philippe Mathieu-Daudé
2025-05-09  6:49   ` Xiaoyao Li
2025-05-09  7:32     ` Zhao Liu
2025-05-09 10:04       ` How to mark internal properties (was: Re: [PATCH v4 12/27] target/i386/cpu: Remove CPUX86State::enable_cpuid_0xb field) Thomas Huth
2025-05-12  2:45         ` Zhao Liu
2025-05-12  6:34         ` How to mark internal properties Markus Armbruster
2025-05-12  8:46         ` How to mark internal properties (was: Re: [PATCH v4 12/27] target/i386/cpu: Remove CPUX86State::enable_cpuid_0xb field) Peter Maydell
2025-05-12  9:06           ` Daniel P. Berrangé
2025-05-12 10:54             ` How to mark internal properties Markus Armbruster
2025-05-12 13:33               ` Xiaoyao Li
2025-05-12 14:41                 ` BALATON Zoltan
2025-05-13  8:16                   ` Thomas Huth
2025-05-12 14:48               ` Mark Cave-Ayland
2025-05-13  8:18                 ` Markus Armbruster
2025-05-13  9:26                   ` BALATON Zoltan
2025-05-13  9:32                     ` Daniel P. Berrangé
2025-05-13 10:38                       ` Markus Armbruster
2025-05-13 11:01                     ` Markus Armbruster
2025-05-26  8:58                     ` Markus Armbruster
2025-05-12 15:22               ` Igor Mammedov
2025-05-13  8:08                 ` Markus Armbruster
2025-05-12 15:00       ` [PATCH v4 12/27] target/i386/cpu: Remove CPUX86State::enable_cpuid_0xb field Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 13/27] target/i386/cpu: Remove CPUX86State::fill_mtrr_mask field Philippe Mathieu-Daudé
2025-05-09  9:30   ` Zhao Liu
2025-05-12 15:24   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 14/27] hw/intc/apic: Remove APICCommonState::legacy_instance_id field Philippe Mathieu-Daudé
2025-05-09  9:30   ` Zhao Liu
2025-05-13  8:34   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 15/27] hw/core/machine: Remove hw_compat_2_6[] array Philippe Mathieu-Daudé
2025-05-09  9:31   ` Zhao Liu
2025-05-13  8:36   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 16/27] hw/virtio/virtio-mmio: Remove VirtIOMMIOProxy::format_transport_address field Philippe Mathieu-Daudé
2025-05-09  9:33   ` Zhao Liu
2025-05-08 13:35 ` [PATCH v4 17/27] hw/i386/pc: Remove deprecated pc-q35-2.7 and pc-i440fx-2.7 machines Philippe Mathieu-Daudé
2025-05-09  9:33   ` Zhao Liu
2025-05-13  8:53   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 18/27] hw/i386/pc: Remove pc_compat_2_7[] array Philippe Mathieu-Daudé
2025-05-09  9:35   ` Zhao Liu
2025-05-08 13:35 ` [PATCH v4 19/27] target/i386/cpu: Remove CPUX86State::full_cpuid_auto_level field Philippe Mathieu-Daudé
2025-05-09  9:37   ` Zhao Liu
2025-05-13 11:02   ` Igor Mammedov [this message]
2025-05-08 13:35 ` [PATCH v4 20/27] target/i386/cpu: Remove CPUX86State::enable_l3_cache field Philippe Mathieu-Daudé
2025-05-09  9:11   ` Zhao Liu
2025-05-13 11:14     ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 21/27] hw/audio/pcspk: Remove PCSpkState::migrate field Philippe Mathieu-Daudé
2025-05-09  9:38   ` Zhao Liu
2025-05-13  9:02   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 22/27] hw/core/machine: Remove hw_compat_2_7[] array Philippe Mathieu-Daudé
2025-05-09  9:38   ` Zhao Liu
2025-05-08 13:35 ` [PATCH v4 23/27] hw/i386/intel_iommu: Remove IntelIOMMUState::buggy_eim field Philippe Mathieu-Daudé
2025-05-09  9:41   ` Zhao Liu
2025-05-13  9:16   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 24/27] hw/intc/ioapic: Remove IOAPICCommonState::version field Philippe Mathieu-Daudé
2025-05-09 10:32   ` Zhao Liu
2025-05-13 10:28   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 25/27] hw/virtio/virtio-pci: Remove VirtIOPCIProxy::ignore_backend_features field Philippe Mathieu-Daudé
2025-05-09  9:43   ` Zhao Liu
2025-05-13 10:30   ` Igor Mammedov
2025-05-08 13:35 ` [PATCH v4 26/27] hw/char/virtio-serial: Do not expose the 'emergency-write' property Philippe Mathieu-Daudé
2025-05-09  9:13   ` Mark Cave-Ayland
2025-05-09  9:46   ` Zhao Liu
2025-05-08 13:35 ` [PATCH v4 27/27] hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_PAGE_PER_VQ definition Philippe Mathieu-Daudé
2025-05-09 10:19   ` Zhao Liu
2025-05-13 10:48   ` Igor Mammedov
2025-05-13 11:23 ` [PATCH v4 00/27] hw/i386/pc: Remove deprecated 2.6 and 2.7 PC machines Igor Mammedov
2025-05-30 11:35   ` Michael S. Tsirkin
2025-05-30 12:08     ` Peter Krempa
2025-05-30 12:50       ` Jiri Denemark
2025-06-17  6:54       ` Zhao Liu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250513130224.3aa2e837@imammedo.users.ipa.redhat.com \
    --to=imammedo@redhat.com \
    --cc=alistair.francis@wdc.com \
    --cc=amit@kernel.org \
    --cc=anisinha@redhat.com \
    --cc=chenhuacai@kernel.org \
    --cc=clement.mathieu--drif@eviden.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=deller@gmx.de \
    --cc=eduardo@habkost.net \
    --cc=farosas@suse.de \
    --cc=jasowang@redhat.com \
    --cc=jiaxun.yang@flygoat.com \
    --cc=kraxel@redhat.com \
    --cc=kvm@vger.kernel.org \
    --cc=liwei1518@gmail.com \
    --cc=lvivier@redhat.com \
    --cc=marcandre.lureau@redhat.com \
    --cc=marcel.apfelbaum@gmail.com \
    --cc=mst@redhat.com \
    --cc=mtosatti@redhat.com \
    --cc=palmer@dabbelt.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=philmd@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=slp@redhat.com \
    --cc=wangyanan55@huawei.com \
    --cc=yi.l.liu@intel.com \
    --cc=zhao1.liu@intel.com \
    --cc=zhiwei_liu@linux.alibaba.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).