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Tsirkin" , Eduardo Habkost , Marcel Apfelbaum , Alistair Francis , Daniel Henrique Barboza , Marcelo Tosatti , qemu-riscv@nongnu.org, Weiwei Li , Amit Shah , Zhao Liu , Yanan Wang , Helge Deller , Palmer Dabbelt , Ani Sinha , Fabiano Rosas , Paolo Bonzini , Liu Zhiwei , =?UTF-8?B?Q2zDqW1lbnQ=?= Mathieu--Drif , qemu-arm@nongnu.org, =?UTF-8?B?TWFyYy1BbmRyw6k=?= Lureau , Huacai Chen , Jason Wang Subject: Re: [PATCH v4 19/27] target/i386/cpu: Remove CPUX86State::full_cpuid_auto_level field Message-ID: <20250513130224.3aa2e837@imammedo.users.ipa.redhat.com> In-Reply-To: <20250508133550.81391-20-philmd@linaro.org> References: <20250508133550.81391-1-philmd@linaro.org> <20250508133550.81391-20-philmd@linaro.org> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.43; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.551, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 8 May 2025 15:35:42 +0200 Philippe Mathieu-Daud=C3=A9 wrote: > The CPUX86State::full_cpuid_auto_level boolean was only > disabled for the pc-q35-2.7 and pc-i440fx-2.7 machines, > which got removed. Being now always %true, we can remove > it and simplify x86_cpu_expand_features(). I've found field being mentioned only by some external rust library, that's likely shouldn't concern QEMU qemu though. I'm not confident enough to ack it but I won't object either =20 > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/i386/cpu.h | 3 -- > target/i386/cpu.c | 106 ++++++++++++++++++++++------------------------ > 2 files changed, 51 insertions(+), 58 deletions(-) >=20 > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 7585407da54..b5cbd91c156 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -2241,9 +2241,6 @@ struct ArchCPU { > */ > bool legacy_multi_node; > =20 > - /* Enable auto level-increase for all CPUID leaves */ > - bool full_cpuid_auto_level; > - > /* Only advertise CPUID leaves defined by the vendor */ > bool vendor_cpuid_only; > =20 > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index fb505d13122..6b9a1f2251a 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -7843,68 +7843,65 @@ void x86_cpu_expand_features(X86CPU *cpu, Error *= *errp) > =20 > /* CPUID[EAX=3D7,ECX=3D0].EBX always increased level automatically: = */ > x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); > - if (cpu->full_cpuid_auto_level) { > - x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); > - x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); > - x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); > - x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); > - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); > - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); > - x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); > - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); > - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); > - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); > - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); > - x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); > - x86_cpu_adjust_feat_level(cpu, FEAT_SVM); > - x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); > + x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); > + x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); > + x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); > + x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); > + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); > + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); > + x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); > + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); > + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); > + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); > + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); > + x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); > + x86_cpu_adjust_feat_level(cpu, FEAT_SVM); > + x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); > =20 > - /* Intel Processor Trace requires CPUID[0x14] */ > - if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { > - if (cpu->intel_pt_auto_level) { > - x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x1= 4); > - } else if (cpu->env.cpuid_min_level < 0x14) { > - mark_unavailable_features(cpu, FEAT_7_0_EBX, > - CPUID_7_0_EBX_INTEL_PT, > - "Intel PT need CPUID leaf 0x14, please set by \"-cpu= ...,intel-pt=3Don,min-level=3D0x14\""); > - } > + /* Intel Processor Trace requires CPUID[0x14] */ > + if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { > + if (cpu->intel_pt_auto_level) { > + x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); > + } else if (cpu->env.cpuid_min_level < 0x14) { > + mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_I= NTEL_PT, > + "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...= ,intel-pt=3Don,min-level=3D0x14\""); > } > + } > =20 > - /* > - * Intel CPU topology with multi-dies support requires CPUID[0x1= F]. > - * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should = detect > - * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, u= nless > - * cpu->vendor_cpuid_only has been unset for compatibility with = older > - * machine types. > - */ > - if (x86_has_extended_topo(env->avail_cpu_topo) && > - (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { > - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); > - } > + /* > + * Intel CPU topology with multi-dies support requires CPUID[0x1F]. > + * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should dete= ct > + * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless > + * cpu->vendor_cpuid_only has been unset for compatibility with older > + * machine types. > + */ > + if (x86_has_extended_topo(env->avail_cpu_topo) && > + (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { > + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); > + } > =20 > - /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ > - if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { > - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); > - } > + /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ > + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { > + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); > + } > =20 > - /* SVM requires CPUID[0x8000000A] */ > - if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { > - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A= ); > - } > + /* SVM requires CPUID[0x8000000A] */ > + if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { > + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); > + } > =20 > - /* SEV requires CPUID[0x8000001F] */ > - if (sev_enabled()) { > - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F= ); > - } > + /* SEV requires CPUID[0x8000001F] */ > + if (sev_enabled()) { > + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); > + } > =20 > - if (env->features[FEAT_8000_0021_EAX]) { > - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021= ); > - } > + if (env->features[FEAT_8000_0021_EAX]) { > + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); > + } > =20 > - /* SGX requires CPUID[0x12] for EPC enumeration */ > - if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { > - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); > - } > + /* SGX requires CPUID[0x12] for EPC enumeration */ > + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { > + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); > } > =20 > /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly se= t */ > @@ -8820,7 +8817,6 @@ static const Property x86_cpu_properties[] =3D { > DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), > DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), > DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), > - DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_le= vel, true), > DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), > DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, t= rue), > DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_= features_only, true),