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Tsirkin" , Eduardo Habkost , Marcel Apfelbaum , Alistair Francis , Daniel Henrique Barboza , Marcelo Tosatti , qemu-riscv@nongnu.org, Weiwei Li , Amit Shah , Yanan Wang , Helge Deller , Palmer Dabbelt , Ani Sinha , Fabiano Rosas , Paolo Bonzini , Liu Zhiwei , =?UTF-8?B?Q2zDqW1lbnQ=?= Mathieu--Drif , qemu-arm@nongnu.org, =?UTF-8?B?TWFy?= =?UTF-8?B?Yy1BbmRyw6k=?= Lureau , Huacai Chen , Jason Wang Subject: Re: [PATCH v4 20/27] target/i386/cpu: Remove CPUX86State::enable_l3_cache field Message-ID: <20250513131439.3ae54224@imammedo.users.ipa.redhat.com> In-Reply-To: References: <20250508133550.81391-1-philmd@linaro.org> <20250508133550.81391-21-philmd@linaro.org> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.43; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.549, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, 9 May 2025 17:11:13 +0800 Zhao Liu wrote: > On Thu, May 08, 2025 at 03:35:43PM +0200, Philippe Mathieu-Daud=C3=A9 wro= te: > > Date: Thu, 8 May 2025 15:35:43 +0200 > > From: Philippe Mathieu-Daud=C3=A9 > > Subject: [PATCH v4 20/27] target/i386/cpu: Remove > > CPUX86State::enable_l3_cache field > > X-Mailer: git-send-email 2.47.1 > >=20 > > The CPUX86State::enable_l3_cache boolean was only disabled > > for the pc-q35-2.7 and pc-i440fx-2.7 machines, which got > > removed. Being now always %true, we can remove it and simplify > > cpu_x86_cpuid() and encode_cache_cpuid80000006(). > >=20 > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > > --- > > target/i386/cpu.h | 6 ------ > > target/i386/cpu.c | 39 +++++++++++++-------------------------- > > 2 files changed, 13 insertions(+), 32 deletions(-) > >=20 > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > > index b5cbd91c156..62239b0a562 100644 > > --- a/target/i386/cpu.h > > +++ b/target/i386/cpu.h > > @@ -2219,12 +2219,6 @@ struct ArchCPU { > > */ > > bool enable_lmce; > > =20 > > - /* Compatibility bits for old machine types. > > - * If true present virtual l3 cache for VM, the vcpus in the same = virtual > > - * socket share an virtual l3 cache. > > - */ > > - bool enable_l3_cache; > > - > > /* Compatibility bits for old machine types. > > * If true present L1 cache as per-thread, not per-core. > > */ =20 >=20 > I realize this is another special case. >=20 > There is no support for hybrid x86 CPUs in QEMU, but it's also true that > there are some actual modern x86 Client CPUs without l3 cache, such as > Intel MTL's low power E core (and it has vmx support, i.e., support KVM). >=20 > So I think we can keep this property as well, to have some more > configuration options for users' emulation. it also seems that libvirt uses it.