From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Fabiano Rosas" <farosas@suse.de>,
"Laurent Vivier" <lvivier@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v3 16/28] hw/misc/aspeed_hace: Support to dump plaintext and digest for better debugging
Date: Thu, 15 May 2025 16:09:48 +0800 [thread overview]
Message-ID: <20250515081008.583578-17-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250515081008.583578-1-jamin_lin@aspeedtech.com>
1. Added "hace_hexdump()" to dump a contiguous buffer using qemu_hexdump.
2. Added "hace_iov_hexdump()" to flatten and dump scatter-gather source vectors.
3. Introduced a new trace event: "aspeed_hace_hexdump".
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_hace.c | 46 +++++++++++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 1 +
2 files changed, 47 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index ee1d9ab58f..8924a30eff 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -10,8 +10,10 @@
*/
#include "qemu/osdep.h"
+#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
+#include "qemu/iov.h"
#include "hw/misc/aspeed_hace.h"
#include "qapi/error.h"
#include "migration/vmstate.h"
@@ -88,6 +90,42 @@ static const struct {
QCRYPTO_HASH_ALGO_SHA256 },
};
+static void hace_hexdump(const char *desc, const char *buf, size_t size)
+{
+ g_autoptr(GString) str = g_string_sized_new(64);
+ size_t len;
+ size_t i;
+
+ for (i = 0; i < size; i += len) {
+ len = MIN(16, size - i);
+ g_string_truncate(str, 0);
+ qemu_hexdump_line(str, buf + i, len, 1, 4);
+ trace_aspeed_hace_hexdump(desc, i, str->str);
+ }
+}
+
+static void hace_iov_hexdump(const char *desc, const struct iovec *iov,
+ const unsigned int iov_cnt)
+{
+ size_t size = 0;
+ char *buf;
+ int i;
+
+ for (i = 0; i < iov_cnt; i++) {
+ size += iov[i].iov_len;
+ }
+
+ buf = g_malloc(size);
+
+ if (!buf) {
+ return;
+ }
+
+ iov_to_buf(iov, iov_cnt, 0, buf, size);
+ hace_hexdump(desc, buf, size);
+ g_free(buf);
+}
+
static int hash_algo_lookup(uint32_t reg)
{
int i;
@@ -302,6 +340,10 @@ static void hash_write_digest_and_unmap_iov(AspeedHACEState *s,
__func__, digest_addr);
}
+ if (trace_event_get_state_backends(TRACE_ASPEED_HACE_HEXDUMP)) {
+ hace_hexdump("digest", (char *)digest_buf, digest_len);
+ }
+
for (; iov_idx > 0; iov_idx--) {
address_space_unmap(&s->dram_as, iov[iov_idx - 1].iov_base,
iov[iov_idx - 1].iov_len, false,
@@ -395,6 +437,10 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
return;
}
+ if (trace_event_get_state_backends(TRACE_ASPEED_HACE_HEXDUMP)) {
+ hace_iov_hexdump("plaintext", iov, iov_idx);
+ }
+
/* Executes the hash operation */
if (acc_mode) {
hash_execute_acc_mode(s, algo, iov, iov_idx, acc_final_request);
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index b980d7fdd3..e3f64c0ff6 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -308,6 +308,7 @@ aspeed_hace_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%
aspeed_hace_hash_sg(int index, uint64_t list_addr, uint64_t buf_addr, uint32_t len) "%d: list_addr 0x%" PRIx64 " buf_addr 0x%" PRIx64 " len 0x%" PRIx32
aspeed_hace_hash_addr(const char *s, uint64_t addr) "%s: 0x%" PRIx64
aspeed_hace_hash_execute_acc_mode(bool final_request) "final request: %d"
+aspeed_hace_hexdump(const char *desc, uint32_t offset, char *s) "%s: 0x%08x: %s"
# bcm2835_property.c
bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu"
--
2.43.0
next prev parent reply other threads:[~2025-05-15 8:12 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-15 8:09 [PATCH v3 00/28] Fix incorrect hash results on AST2700 Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 01/28] hw/misc/aspeed_hace: Remove unused code for better readability Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 02/28] hw/misc/aspeed_hace: Improve readability and consistency in variable naming Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 03/28] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 04/28] hw/misc/aspeed_hace: Extract direct mode hash buffer setup into helper function Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 05/28] hw/misc/aspeed_hace: Extract SG-mode " Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 06/28] hw/misc/aspeed_hace: Extract digest write and iov unmap " Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 07/28] hw/misc/aspeed_hace: Extract non-accumulation hash execution " Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 08/28] hw/misc/aspeed_hace: Extract accumulation-mode " Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 09/28] hw/misc/aspeed_hace: Introduce 64-bit hash source address " Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 10/28] hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST and introduce 64-bit hash digest address helper Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 11/28] hw/misc/aspeed_hace: Support accumulative mode for direct access mode Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 12/28] hw/misc/aspeed_hace: Move register size to instance class and dynamically allocate regs Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 13/28] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 14/28] hw/misc/aspeed_hace: Support DMA 64 bits dram address Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 15/28] hw/misc/aspeed_hace: Add trace-events for better debugging Jamin Lin via
2025-05-15 8:09 ` Jamin Lin via [this message]
2025-05-15 8:09 ` [PATCH v3 17/28] tests/qtest: Reorder aspeed test list Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 18/28] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 19/28] test/qtest/hace: Specify explicit array sizes for test vectors and hash results Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 20/28] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 21/28] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 22/28] test/qtest/hace: Add SHA-384 tests for AST2600 Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 23/28] test/qtest/hace: Add tests for AST1030 Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 24/28] test/qtest/hace: Update source data and digest data type to 64-bit Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 25/28] test/qtest/hace: Support 64-bit source and digest addresses for AST2700 Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 26/28] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Jamin Lin via
2025-05-15 8:09 ` [PATCH v3 27/28] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Jamin Lin via
2025-05-15 8:10 ` [PATCH v3 28/28] test/qtest/hace: Add tests for AST2700 Jamin Lin via
2025-05-20 14:58 ` [PATCH v3 00/28] Fix incorrect hash results on AST2700 Fabiano Rosas
2025-05-23 7:17 ` Cédric Le Goater
2025-05-23 8:10 ` Cédric Le Goater
2025-05-29 7:29 ` Michael Tokarev
2025-05-29 7:38 ` Cédric Le Goater
2025-05-29 7:40 ` Jamin Lin
2025-05-29 7:45 ` Michael Tokarev
2025-05-29 12:17 ` Cédric Le Goater
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