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Tue, 20 May 2025 04:06:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHowjTnT4qH12nfh2SsatRXCk76ngau5dw3EnjDcTdPH+FYVOYQuz5sNvsJyZeBJklvU6GDdA== X-Received: by 2002:a17:907:7291:b0:ad1:dbec:44d3 with SMTP id a640c23a62f3a-ad536bdf275mr1473385466b.27.1747739175608; Tue, 20 May 2025 04:06:15 -0700 (PDT) Received: from [192.168.122.1] ([151.95.46.79]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d4908cesm717662466b.132.2025.05.20.04.06.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 May 2025 04:06:14 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Alistair Francis Subject: [PULL 19/35] target/riscv: include default value in cpu_cfg_fields.h.inc Date: Tue, 20 May 2025 13:05:14 +0200 Message-ID: <20250520110530.366202-20-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250520110530.366202-1-pbonzini@redhat.com> References: <20250520110530.366202-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.487, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation for adding a function to merge two RISCVCPUConfigs (pulling values from the parent if they are not overridden) annotate cpu_cfg_fields.h.inc with the default value of the fields. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h | 2 +- target/riscv/cpu_cfg_fields.h.inc | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e9bf75730a6..aa28dc8d7e6 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -23,7 +23,7 @@ struct RISCVCPUConfig { #define BOOL_FIELD(x) bool x; -#define TYPED_FIELD(type, x) type x; +#define TYPED_FIELD(type, x, default) type x; #include "cpu_cfg_fields.h.inc" }; diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc index cb86bfc5dc3..59f134a4192 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -2,7 +2,7 @@ * Required definitions before including this file: * * #define BOOL_FIELD(x) - * #define TYPED_FIELD(type, x) + * #define TYPED_FIELD(type, x, default) */ BOOL_FIELD(ext_zba) @@ -153,18 +153,18 @@ BOOL_FIELD(misa_w) BOOL_FIELD(short_isa_string) -TYPED_FIELD(uint32_t, mvendorid) -TYPED_FIELD(uint64_t, marchid) -TYPED_FIELD(uint64_t, mimpid) +TYPED_FIELD(uint32_t, mvendorid, 0) +TYPED_FIELD(uint64_t, marchid, 0) +TYPED_FIELD(uint64_t, mimpid, 0) -TYPED_FIELD(uint32_t, pmu_mask) -TYPED_FIELD(uint16_t, vlenb) -TYPED_FIELD(uint16_t, elen) -TYPED_FIELD(uint16_t, cbom_blocksize) -TYPED_FIELD(uint16_t, cbop_blocksize) -TYPED_FIELD(uint16_t, cboz_blocksize) +TYPED_FIELD(uint32_t, pmu_mask, 0) +TYPED_FIELD(uint16_t, vlenb, 0) +TYPED_FIELD(uint16_t, elen, 0) +TYPED_FIELD(uint16_t, cbom_blocksize, 0) +TYPED_FIELD(uint16_t, cbop_blocksize, 0) +TYPED_FIELD(uint16_t, cboz_blocksize, 0) -TYPED_FIELD(int8_t, max_satp_mode) +TYPED_FIELD(int8_t, max_satp_mode, -1) #undef BOOL_FIELD #undef TYPED_FIELD -- 2.49.0