From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>
Subject: [PULL 06/35] qapi/misc-target: Rename SGXInfo to SgxInfo
Date: Tue, 20 May 2025 13:05:01 +0200 [thread overview]
Message-ID: <20250520110530.366202-7-pbonzini@redhat.com> (raw)
In-Reply-To: <20250520110530.366202-1-pbonzini@redhat.com>
From: Zhao Liu <zhao1.liu@intel.com>
QAPI requires strict PascalCase naming style, i.e., only the first
letter of a single word is allowed to be uppercase, which could help
with readability.
Rename SGXInfo to SgxInfo.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250516091130.2374221-3-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
qapi/misc-target.json | 12 ++++++------
hw/i386/sgx-stub.c | 4 ++--
hw/i386/sgx.c | 14 +++++++-------
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/qapi/misc-target.json b/qapi/misc-target.json
index a1275d3873a..6b3c9d8bd58 100644
--- a/qapi/misc-target.json
+++ b/qapi/misc-target.json
@@ -334,7 +334,7 @@
'size': 'uint64'}}
##
-# @SGXInfo:
+# @SgxInfo:
#
# Information about intel Safe Guard eXtension (SGX) support
#
@@ -350,7 +350,7 @@
#
# Since: 6.2
##
-{ 'struct': 'SGXInfo',
+{ 'struct': 'SgxInfo',
'data': { 'sgx': 'bool',
'sgx1': 'bool',
'sgx2': 'bool',
@@ -363,7 +363,7 @@
#
# Returns information about SGX
#
-# Returns: @SGXInfo
+# Returns: @SgxInfo
#
# Since: 6.2
#
@@ -375,14 +375,14 @@
# "sections": [{"node": 0, "size": 67108864},
# {"node": 1, "size": 29360128}]} }
##
-{ 'command': 'query-sgx', 'returns': 'SGXInfo', 'if': 'TARGET_I386' }
+{ 'command': 'query-sgx', 'returns': 'SgxInfo', 'if': 'TARGET_I386' }
##
# @query-sgx-capabilities:
#
# Returns information from host SGX capabilities
#
-# Returns: @SGXInfo
+# Returns: @SgxInfo
#
# Since: 6.2
#
@@ -394,7 +394,7 @@
# "section" : [{"node": 0, "size": 67108864},
# {"node": 1, "size": 29360128}]} }
##
-{ 'command': 'query-sgx-capabilities', 'returns': 'SGXInfo', 'if': 'TARGET_I386' }
+{ 'command': 'query-sgx-capabilities', 'returns': 'SgxInfo', 'if': 'TARGET_I386' }
##
diff --git a/hw/i386/sgx-stub.c b/hw/i386/sgx-stub.c
index 38ff75e9f37..ccb21a975d7 100644
--- a/hw/i386/sgx-stub.c
+++ b/hw/i386/sgx-stub.c
@@ -10,13 +10,13 @@ void sgx_epc_build_srat(GArray *table_data)
{
}
-SGXInfo *qmp_query_sgx(Error **errp)
+SgxInfo *qmp_query_sgx(Error **errp)
{
error_setg(errp, "SGX support is not compiled in");
return NULL;
}
-SGXInfo *qmp_query_sgx_capabilities(Error **errp)
+SgxInfo *qmp_query_sgx_capabilities(Error **errp)
{
error_setg(errp, "SGX support is not compiled in");
return NULL;
diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
index 3c601689eb7..c80203b438e 100644
--- a/hw/i386/sgx.c
+++ b/hw/i386/sgx.c
@@ -153,9 +153,9 @@ static void sgx_epc_reset(void *opaque)
}
}
-SGXInfo *qmp_query_sgx_capabilities(Error **errp)
+SgxInfo *qmp_query_sgx_capabilities(Error **errp)
{
- SGXInfo *info = NULL;
+ SgxInfo *info = NULL;
uint32_t eax, ebx, ecx, edx;
Error *local_err = NULL;
@@ -166,7 +166,7 @@ SGXInfo *qmp_query_sgx_capabilities(Error **errp)
return NULL;
}
- info = g_new0(SGXInfo, 1);
+ info = g_new0(SgxInfo, 1);
host_cpuid(0x7, 0, &eax, &ebx, &ecx, &edx);
info->sgx = ebx & (1U << 2) ? true : false;
@@ -205,9 +205,9 @@ static SgxEpcSectionList *sgx_get_epc_sections_list(void)
return head;
}
-SGXInfo *qmp_query_sgx(Error **errp)
+SgxInfo *qmp_query_sgx(Error **errp)
{
- SGXInfo *info = NULL;
+ SgxInfo *info = NULL;
X86MachineState *x86ms;
PCMachineState *pcms =
(PCMachineState *)object_dynamic_cast(qdev_get_machine(),
@@ -223,7 +223,7 @@ SGXInfo *qmp_query_sgx(Error **errp)
return NULL;
}
- info = g_new0(SGXInfo, 1);
+ info = g_new0(SgxInfo, 1);
info->sgx = true;
info->sgx1 = true;
@@ -238,7 +238,7 @@ void hmp_info_sgx(Monitor *mon, const QDict *qdict)
{
Error *err = NULL;
SgxEpcSectionList *section_list, *section;
- g_autoptr(SGXInfo) info = qmp_query_sgx(&err);
+ g_autoptr(SgxInfo) info = qmp_query_sgx(&err);
uint64_t size = 0;
if (err) {
--
2.49.0
next prev parent reply other threads:[~2025-05-20 11:06 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 11:04 [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Paolo Bonzini
2025-05-20 11:04 ` [PULL 01/35] i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 02/35] i386/hvf: Make CPUID_HT supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 03/35] hw/pci-host/gt64120: Fix endianness handling Paolo Bonzini
2025-05-20 11:04 ` [PULL 04/35] hw/pci-host: Remove unused pci_host_data_be_ops Paolo Bonzini
2025-05-20 11:05 ` [PULL 05/35] qapi/misc-target: Rename SGXEPCSection to SgxEpcSection Paolo Bonzini
2025-05-20 11:05 ` Paolo Bonzini [this message]
2025-05-20 11:05 ` [PULL 07/35] qapi/misc-target: Fix the doc related SGXEPCSection Paolo Bonzini
2025-05-20 11:05 ` [PULL 08/35] qapi/misc-target: Fix the doc to distinguish query-sgx and query-sgx-capabilities Paolo Bonzini
2025-05-20 11:05 ` [PULL 09/35] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-05-20 11:05 ` [PULL 10/35] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-05-20 11:05 ` [PULL 11/35] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-05-20 11:05 ` [PULL 12/35] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-05-20 11:05 ` [PULL 13/35] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-05-20 11:05 ` [PULL 14/35] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-05-20 11:05 ` [PULL 15/35] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 16/35] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-05-20 11:05 ` [PULL 17/35] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-05-20 11:05 ` [PULL 18/35] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-05-20 11:05 ` [PULL 19/35] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-05-20 11:05 ` [PULL 20/35] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-05-20 11:05 ` [PULL 21/35] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 22/35] target/riscv: convert profile CPU models " Paolo Bonzini
2025-05-20 11:05 ` [PULL 23/35] target/riscv: convert bare " Paolo Bonzini
2025-05-20 11:05 ` [PULL 24/35] target/riscv: convert dynamic " Paolo Bonzini
2025-05-20 11:05 ` [PULL 25/35] target/riscv: convert SiFive E " Paolo Bonzini
2025-05-20 11:05 ` [PULL 26/35] target/riscv: convert ibex " Paolo Bonzini
2025-05-20 11:05 ` [PULL 27/35] target/riscv: convert SiFive U " Paolo Bonzini
2025-05-20 11:05 ` [PULL 28/35] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-05-20 11:05 ` [PULL 29/35] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-05-20 11:05 ` [PULL 30/35] target/riscv: convert THead C906 to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 31/35] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-05-20 11:05 ` [PULL 32/35] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-05-20 11:05 ` [PULL 33/35] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-05-20 11:05 ` [PULL 34/35] target/riscv: remove .instance_post_init Paolo Bonzini
2025-05-20 11:05 ` [PULL 35/35] qom: reverse order of instance_post_init calls Paolo Bonzini
2025-06-23 16:56 ` [Regression] " Dongli Zhang
2025-06-24 8:57 ` Zhao Liu
2025-06-30 15:22 ` Zhao Liu
2025-07-01 6:50 ` Xiaoyao Li
2025-07-02 6:54 ` Philippe Mathieu-Daudé
2025-07-02 7:56 ` Zhao Liu
2025-07-02 11:42 ` Xiaoyao Li
2025-07-02 12:12 ` Paolo Bonzini
2025-07-02 13:24 ` Xiaoyao Li
2025-07-02 18:54 ` Paolo Bonzini
2025-07-03 1:03 ` Xiaoyao Li
2025-07-03 3:08 ` Zhao Liu
2025-07-03 3:36 ` Xiaoyao Li
2025-07-03 4:51 ` Paolo Bonzini
2025-07-07 15:41 ` Paolo Bonzini
2025-07-02 12:06 ` Paolo Bonzini
2025-05-21 14:06 ` [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Stefan Hajnoczi
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