From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>, Markus Armbruster <armbru@redhat.com>
Subject: [PULL 07/35] qapi/misc-target: Fix the doc related SGXEPCSection
Date: Tue, 20 May 2025 13:05:02 +0200 [thread overview]
Message-ID: <20250520110530.366202-8-pbonzini@redhat.com> (raw)
In-Reply-To: <20250520110530.366202-1-pbonzini@redhat.com>
From: Zhao Liu <zhao1.liu@intel.com>
The "sections" field of SGXInfo is used to gather EPC section
information for both the guest and the host. Therefore, delete the "for
guest" limitation.
Additionally, avoid the abbreviation "info" and use "information"
instead. And for SGXEPCSection, delete the redundant word "info".
Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Link: https://lore.kernel.org/r/20250513143131.2008078-2-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
qapi/misc-target.json | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qapi/misc-target.json b/qapi/misc-target.json
index 6b3c9d8bd58..6814708972d 100644
--- a/qapi/misc-target.json
+++ b/qapi/misc-target.json
@@ -321,7 +321,7 @@
##
# @SgxEpcSection:
#
-# Information about intel SGX EPC section info
+# Information about intel SGX EPC section
#
# @node: the numa node
#
@@ -346,7 +346,7 @@
#
# @flc: true if FLC is supported
#
-# @sections: The EPC sections info for guest (Since: 7.0)
+# @sections: The EPC sections information (Since: 7.0)
#
# Since: 6.2
##
--
2.49.0
next prev parent reply other threads:[~2025-05-20 11:10 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 11:04 [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Paolo Bonzini
2025-05-20 11:04 ` [PULL 01/35] i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 02/35] i386/hvf: Make CPUID_HT supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 03/35] hw/pci-host/gt64120: Fix endianness handling Paolo Bonzini
2025-05-20 11:04 ` [PULL 04/35] hw/pci-host: Remove unused pci_host_data_be_ops Paolo Bonzini
2025-05-20 11:05 ` [PULL 05/35] qapi/misc-target: Rename SGXEPCSection to SgxEpcSection Paolo Bonzini
2025-05-20 11:05 ` [PULL 06/35] qapi/misc-target: Rename SGXInfo to SgxInfo Paolo Bonzini
2025-05-20 11:05 ` Paolo Bonzini [this message]
2025-05-20 11:05 ` [PULL 08/35] qapi/misc-target: Fix the doc to distinguish query-sgx and query-sgx-capabilities Paolo Bonzini
2025-05-20 11:05 ` [PULL 09/35] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-05-20 11:05 ` [PULL 10/35] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-05-20 11:05 ` [PULL 11/35] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-05-20 11:05 ` [PULL 12/35] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-05-20 11:05 ` [PULL 13/35] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-05-20 11:05 ` [PULL 14/35] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-05-20 11:05 ` [PULL 15/35] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 16/35] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-05-20 11:05 ` [PULL 17/35] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-05-20 11:05 ` [PULL 18/35] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-05-20 11:05 ` [PULL 19/35] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-05-20 11:05 ` [PULL 20/35] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-05-20 11:05 ` [PULL 21/35] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 22/35] target/riscv: convert profile CPU models " Paolo Bonzini
2025-05-20 11:05 ` [PULL 23/35] target/riscv: convert bare " Paolo Bonzini
2025-05-20 11:05 ` [PULL 24/35] target/riscv: convert dynamic " Paolo Bonzini
2025-05-20 11:05 ` [PULL 25/35] target/riscv: convert SiFive E " Paolo Bonzini
2025-05-20 11:05 ` [PULL 26/35] target/riscv: convert ibex " Paolo Bonzini
2025-05-20 11:05 ` [PULL 27/35] target/riscv: convert SiFive U " Paolo Bonzini
2025-05-20 11:05 ` [PULL 28/35] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-05-20 11:05 ` [PULL 29/35] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-05-20 11:05 ` [PULL 30/35] target/riscv: convert THead C906 to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 31/35] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-05-20 11:05 ` [PULL 32/35] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-05-20 11:05 ` [PULL 33/35] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-05-20 11:05 ` [PULL 34/35] target/riscv: remove .instance_post_init Paolo Bonzini
2025-05-20 11:05 ` [PULL 35/35] qom: reverse order of instance_post_init calls Paolo Bonzini
2025-06-23 16:56 ` [Regression] " Dongli Zhang
2025-06-24 8:57 ` Zhao Liu
2025-06-30 15:22 ` Zhao Liu
2025-07-01 6:50 ` Xiaoyao Li
2025-07-02 6:54 ` Philippe Mathieu-Daudé
2025-07-02 7:56 ` Zhao Liu
2025-07-02 11:42 ` Xiaoyao Li
2025-07-02 12:12 ` Paolo Bonzini
2025-07-02 13:24 ` Xiaoyao Li
2025-07-02 18:54 ` Paolo Bonzini
2025-07-03 1:03 ` Xiaoyao Li
2025-07-03 3:08 ` Zhao Liu
2025-07-03 3:36 ` Xiaoyao Li
2025-07-03 4:51 ` Paolo Bonzini
2025-07-07 15:41 ` Paolo Bonzini
2025-07-02 12:06 ` Paolo Bonzini
2025-05-21 14:06 ` [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Stefan Hajnoczi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250520110530.366202-8-pbonzini@redhat.com \
--to=pbonzini@redhat.com \
--cc=armbru@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=zhao1.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).