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Wed, 21 May 2025 16:55:03 +0100 From: Ben Dooks To: nazar.kazakov@codethink.co.uk, joseph.baker@codethink.co.uk, fran.redondo@codethink.co.uk, lawrence.hunter@codethink.co.uk, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, qemu-riscv@nongnu.org Cc: ben.dooks@codethink.co.uk, qemu-devel@nongnu.org Subject: [PATCH 2/2] target/riscv: add cva6 cpu type Date: Wed, 21 May 2025 16:54:58 +0100 Message-Id: <20250521155458.24255-3-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.37.2.352.g3c44437643 In-Reply-To: <20250521155458.24255-1-ben.dooks@codethink.co.uk> References: <20250521155458.24255-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=78.40.148.171; envelope-from=srv_ts003@codethink.com; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add CVA6 CPU type, for the OpenHW CVA6 cores Signed-off-by: Ben Dooks --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 4cfdb74891..b5460771d7 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -34,6 +34,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_CVA6 RISCV_CPU_TYPE_NAME("cva6") #define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i") #define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e") #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d92874baa0..0ad6a7b616 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -496,6 +496,24 @@ static void rv64_base_cpu_init(Object *obj) #endif } +static void rv64_cva6_cpu_init(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; + + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVS | RVU); + env->priv_ver = PRIV_VERSION_1_12_0; +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); +#endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_zifencei = true; + cpu->cfg.ext_zicsr = true; + cpu->cfg.mmu = true; + cpu->cfg.pmp = true; +} + static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); @@ -3247,6 +3265,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { #if defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_CVA6, MXL_RV64, rv64_cva6_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init), -- 2.37.2.352.g3c44437643