From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E . Iglesias" <edgar.iglesias@amd.com>
Subject: [PULL 10/28] target/microblaze: Fix printf format in mmu_translate
Date: Wed, 28 May 2025 09:13:52 +0100 [thread overview]
Message-ID: <20250528081410.157251-11-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250528081410.157251-1-richard.henderson@linaro.org>
Use TARGET_FMT_lx to match the target_ulong type of vaddr.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 95a12e16f8..8703ff5c65 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -172,7 +172,8 @@ unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
}
done:
qemu_log_mask(CPU_LOG_MMU,
- "MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
+ "MMU vaddr=0x" TARGET_FMT_lx
+ " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
vaddr, rw, tlb_wr, tlb_ex, hit);
return hit;
}
--
2.43.0
next prev parent reply other threads:[~2025-05-28 8:15 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-28 8:13 [PULL 00/28] tcg patch queue Richard Henderson
2025-05-28 8:13 ` [PULL 01/28] accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW Richard Henderson
2025-05-28 8:13 ` [PULL 02/28] system/main: comment lock rationale Richard Henderson
2025-05-28 8:13 ` [PULL 03/28] linux-user: implement pgid field of /proc/self/stat Richard Henderson
2025-05-28 8:13 ` [PULL 04/28] target/microblaze: Split out mb_unaligned_access_internal Richard Henderson
2025-05-28 8:13 ` [PULL 05/28] target/microblaze: Introduce helper_unaligned_access Richard Henderson
2025-05-28 8:13 ` [PULL 06/28] target/microblaze: Split out mb_transaction_failed_internal Richard Henderson
2025-05-28 8:13 ` [PULL 07/28] target/microblaze: Implement extended address load/store out of line Richard Henderson
2025-05-28 8:13 ` [PULL 08/28] target/microblaze: Use uint64_t for CPUMBState.ear Richard Henderson
2025-05-28 8:13 ` [PULL 09/28] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea Richard Henderson
2025-05-28 8:13 ` Richard Henderson [this message]
2025-05-28 8:13 ` [PULL 11/28] target/microblaze: Use TARGET_LONG_BITS == 32 for system mode Richard Henderson
2025-05-28 8:13 ` [PULL 12/28] target/microblaze: Drop DisasContext.r0 Richard Henderson
2025-05-28 8:13 ` [PULL 13/28] target/microblaze: Simplify compute_ldst_addr_type{a,b} Richard Henderson
2025-05-28 8:13 ` [PULL 14/28] tcg: Drop TCGContext.tlb_dyn_max_bits Richard Henderson
2025-05-28 8:13 ` [PULL 15/28] tcg: Drop TCGContext.page_{mask,bits} Richard Henderson
2025-05-28 8:13 ` [PULL 16/28] target/sh4: Use MO_ALIGN for system UNALIGN() Richard Henderson
2025-05-28 8:13 ` [PULL 17/28] accel/tcg: Add TCGCPUOps.pointer_wrap Richard Henderson
2025-05-28 8:14 ` [PULL 18/28] target: Use cpu_pointer_wrap_notreached for strict align targets Richard Henderson
2025-08-29 6:55 ` Michael Tokarev
2025-08-30 3:11 ` Richard Henderson
2025-05-28 8:14 ` [PULL 19/28] target: Use cpu_pointer_wrap_uint32 for 32-bit targets Richard Henderson
2025-05-28 8:14 ` [PULL 20/28] target/arm: Fill in TCGCPUOps.pointer_wrap Richard Henderson
2025-05-28 8:14 ` [PULL 21/28] target/i386: " Richard Henderson
2025-05-28 8:14 ` [PULL 22/28] target/loongarch: " Richard Henderson
2025-05-28 8:14 ` [PULL 23/28] target/mips: " Richard Henderson
2025-05-28 8:14 ` [PULL 24/28] target/ppc: " Richard Henderson
2025-05-28 8:14 ` [PULL 25/28] target/riscv: " Richard Henderson
2025-05-28 8:14 ` [PULL 26/28] target/s390x: " Richard Henderson
2025-05-28 8:14 ` [PULL 27/28] target/sparc: " Richard Henderson
2025-05-28 8:14 ` [PULL 28/28] accel/tcg: Assert TCGCPUOps.pointer_wrap is set Richard Henderson
2025-05-29 12:35 ` [PULL 00/28] tcg patch queue Stefan Hajnoczi
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