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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 27/28] target/sparc: Fill in TCGCPUOps.pointer_wrap
Date: Wed, 28 May 2025 09:14:09 +0100	[thread overview]
Message-ID: <20250528081410.157251-28-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250528081410.157251-1-richard.henderson@linaro.org>

Check address masking state for sparc64.

Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/cpu.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 2a3e408923..ed7701b02f 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1002,6 +1002,18 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
 #ifdef CONFIG_TCG
 #include "accel/tcg/cpu-ops.h"
 
+#ifndef CONFIG_USER_ONLY
+static vaddr sparc_pointer_wrap(CPUState *cs, int mmu_idx,
+                                vaddr result, vaddr base)
+{
+#ifdef TARGET_SPARC64
+    return cpu_env(cs)->pstate & PS_AM ? (uint32_t)result : result;
+#else
+    return (uint32_t)result;
+#endif
+}
+#endif
+
 static const TCGCPUOps sparc_tcg_ops = {
     /*
      * From Oracle SPARC Architecture 2015:
@@ -1036,6 +1048,7 @@ static const TCGCPUOps sparc_tcg_ops = {
 
 #ifndef CONFIG_USER_ONLY
     .tlb_fill = sparc_cpu_tlb_fill,
+    .pointer_wrap = sparc_pointer_wrap,
     .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
     .cpu_exec_halt = sparc_cpu_has_work,
     .cpu_exec_reset = cpu_reset,
-- 
2.43.0



  parent reply	other threads:[~2025-05-28  8:17 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-28  8:13 [PULL 00/28] tcg patch queue Richard Henderson
2025-05-28  8:13 ` [PULL 01/28] accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW Richard Henderson
2025-05-28  8:13 ` [PULL 02/28] system/main: comment lock rationale Richard Henderson
2025-05-28  8:13 ` [PULL 03/28] linux-user: implement pgid field of /proc/self/stat Richard Henderson
2025-05-28  8:13 ` [PULL 04/28] target/microblaze: Split out mb_unaligned_access_internal Richard Henderson
2025-05-28  8:13 ` [PULL 05/28] target/microblaze: Introduce helper_unaligned_access Richard Henderson
2025-05-28  8:13 ` [PULL 06/28] target/microblaze: Split out mb_transaction_failed_internal Richard Henderson
2025-05-28  8:13 ` [PULL 07/28] target/microblaze: Implement extended address load/store out of line Richard Henderson
2025-05-28  8:13 ` [PULL 08/28] target/microblaze: Use uint64_t for CPUMBState.ear Richard Henderson
2025-05-28  8:13 ` [PULL 09/28] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea Richard Henderson
2025-05-28  8:13 ` [PULL 10/28] target/microblaze: Fix printf format in mmu_translate Richard Henderson
2025-05-28  8:13 ` [PULL 11/28] target/microblaze: Use TARGET_LONG_BITS == 32 for system mode Richard Henderson
2025-05-28  8:13 ` [PULL 12/28] target/microblaze: Drop DisasContext.r0 Richard Henderson
2025-05-28  8:13 ` [PULL 13/28] target/microblaze: Simplify compute_ldst_addr_type{a,b} Richard Henderson
2025-05-28  8:13 ` [PULL 14/28] tcg: Drop TCGContext.tlb_dyn_max_bits Richard Henderson
2025-05-28  8:13 ` [PULL 15/28] tcg: Drop TCGContext.page_{mask,bits} Richard Henderson
2025-05-28  8:13 ` [PULL 16/28] target/sh4: Use MO_ALIGN for system UNALIGN() Richard Henderson
2025-05-28  8:13 ` [PULL 17/28] accel/tcg: Add TCGCPUOps.pointer_wrap Richard Henderson
2025-05-28  8:14 ` [PULL 18/28] target: Use cpu_pointer_wrap_notreached for strict align targets Richard Henderson
2025-08-29  6:55   ` Michael Tokarev
2025-08-30  3:11     ` Richard Henderson
2025-05-28  8:14 ` [PULL 19/28] target: Use cpu_pointer_wrap_uint32 for 32-bit targets Richard Henderson
2025-05-28  8:14 ` [PULL 20/28] target/arm: Fill in TCGCPUOps.pointer_wrap Richard Henderson
2025-05-28  8:14 ` [PULL 21/28] target/i386: " Richard Henderson
2025-05-28  8:14 ` [PULL 22/28] target/loongarch: " Richard Henderson
2025-05-28  8:14 ` [PULL 23/28] target/mips: " Richard Henderson
2025-05-28  8:14 ` [PULL 24/28] target/ppc: " Richard Henderson
2025-05-28  8:14 ` [PULL 25/28] target/riscv: " Richard Henderson
2025-05-28  8:14 ` [PULL 26/28] target/s390x: " Richard Henderson
2025-05-28  8:14 ` Richard Henderson [this message]
2025-05-28  8:14 ` [PULL 28/28] accel/tcg: Assert TCGCPUOps.pointer_wrap is set Richard Henderson
2025-05-29 12:35 ` [PULL 00/28] tcg patch queue Stefan Hajnoczi

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