From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E . Iglesias" <edgar.iglesias@amd.com>
Subject: [PULL 05/28] target/microblaze: Introduce helper_unaligned_access
Date: Wed, 28 May 2025 09:13:47 +0100 [thread overview]
Message-ID: <20250528081410.157251-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250528081410.157251-1-richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/helper.h | 12 ++++++------
target/microblaze/helper.c | 7 +++++++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
index f740835fcb..41f56a5601 100644
--- a/target/microblaze/helper.h
+++ b/target/microblaze/helper.h
@@ -20,12 +20,12 @@ DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32)
-#if !defined(CONFIG_USER_ONLY)
-DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32)
-DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32)
-#endif
-
DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl)
-
DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32)
DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32)
+
+#ifndef CONFIG_USER_ONLY
+DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32)
+DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32)
+DEF_HELPER_FLAGS_2(unaligned_access, TCG_CALL_NO_WG, noreturn, env, i64)
+#endif
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 5fe81e4b16..ef0e2f973f 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -26,6 +26,7 @@
#include "exec/target_page.h"
#include "qemu/host-utils.h"
#include "exec/log.h"
+#include "exec/helper-proto.h"
G_NORETURN
@@ -64,6 +65,12 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
}
#ifndef CONFIG_USER_ONLY
+
+void HELPER(unaligned_access)(CPUMBState *env, uint64_t addr)
+{
+ mb_unaligned_access_internal(env_cpu(env), addr, GETPC());
+}
+
static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
MMUAccessType access_type)
{
--
2.43.0
next prev parent reply other threads:[~2025-05-28 8:17 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-28 8:13 [PULL 00/28] tcg patch queue Richard Henderson
2025-05-28 8:13 ` [PULL 01/28] accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW Richard Henderson
2025-05-28 8:13 ` [PULL 02/28] system/main: comment lock rationale Richard Henderson
2025-05-28 8:13 ` [PULL 03/28] linux-user: implement pgid field of /proc/self/stat Richard Henderson
2025-05-28 8:13 ` [PULL 04/28] target/microblaze: Split out mb_unaligned_access_internal Richard Henderson
2025-05-28 8:13 ` Richard Henderson [this message]
2025-05-28 8:13 ` [PULL 06/28] target/microblaze: Split out mb_transaction_failed_internal Richard Henderson
2025-05-28 8:13 ` [PULL 07/28] target/microblaze: Implement extended address load/store out of line Richard Henderson
2025-05-28 8:13 ` [PULL 08/28] target/microblaze: Use uint64_t for CPUMBState.ear Richard Henderson
2025-05-28 8:13 ` [PULL 09/28] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea Richard Henderson
2025-05-28 8:13 ` [PULL 10/28] target/microblaze: Fix printf format in mmu_translate Richard Henderson
2025-05-28 8:13 ` [PULL 11/28] target/microblaze: Use TARGET_LONG_BITS == 32 for system mode Richard Henderson
2025-05-28 8:13 ` [PULL 12/28] target/microblaze: Drop DisasContext.r0 Richard Henderson
2025-05-28 8:13 ` [PULL 13/28] target/microblaze: Simplify compute_ldst_addr_type{a,b} Richard Henderson
2025-05-28 8:13 ` [PULL 14/28] tcg: Drop TCGContext.tlb_dyn_max_bits Richard Henderson
2025-05-28 8:13 ` [PULL 15/28] tcg: Drop TCGContext.page_{mask,bits} Richard Henderson
2025-05-28 8:13 ` [PULL 16/28] target/sh4: Use MO_ALIGN for system UNALIGN() Richard Henderson
2025-05-28 8:13 ` [PULL 17/28] accel/tcg: Add TCGCPUOps.pointer_wrap Richard Henderson
2025-05-28 8:14 ` [PULL 18/28] target: Use cpu_pointer_wrap_notreached for strict align targets Richard Henderson
2025-08-29 6:55 ` Michael Tokarev
2025-08-30 3:11 ` Richard Henderson
2025-05-28 8:14 ` [PULL 19/28] target: Use cpu_pointer_wrap_uint32 for 32-bit targets Richard Henderson
2025-05-28 8:14 ` [PULL 20/28] target/arm: Fill in TCGCPUOps.pointer_wrap Richard Henderson
2025-05-28 8:14 ` [PULL 21/28] target/i386: " Richard Henderson
2025-05-28 8:14 ` [PULL 22/28] target/loongarch: " Richard Henderson
2025-05-28 8:14 ` [PULL 23/28] target/mips: " Richard Henderson
2025-05-28 8:14 ` [PULL 24/28] target/ppc: " Richard Henderson
2025-05-28 8:14 ` [PULL 25/28] target/riscv: " Richard Henderson
2025-05-28 8:14 ` [PULL 26/28] target/s390x: " Richard Henderson
2025-05-28 8:14 ` [PULL 27/28] target/sparc: " Richard Henderson
2025-05-28 8:14 ` [PULL 28/28] accel/tcg: Assert TCGCPUOps.pointer_wrap is set Richard Henderson
2025-05-29 12:35 ` [PULL 00/28] tcg patch queue Stefan Hajnoczi
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