* [PULL 01/27] tests/functional/test_sparc64_tuxrun: Explicitly set the 'sun4u' machine
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 02/27] tests/functional/test_mips_malta: Re-enable the check for the PCI host bridge Thomas Huth
` (26 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Stefan Hajnoczi, Alex Bennée
From: Thomas Huth <thuth@redhat.com>
Use self.set_machine() to set the machine instead of relying on the
default machine of the binary. This way the test can be skipped in
case the machine has not been compiled into the QEMU binary.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250521145112.142222-1-thuth@redhat.com>
---
tests/functional/test_sparc64_tuxrun.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/functional/test_sparc64_tuxrun.py b/tests/functional/test_sparc64_tuxrun.py
index 3be08d6102b..0d7b43dd74c 100755
--- a/tests/functional/test_sparc64_tuxrun.py
+++ b/tests/functional/test_sparc64_tuxrun.py
@@ -24,6 +24,7 @@ class TuxRunSparc64Test(TuxRunBaselineTest):
'479c3dc104c82b68be55e2c0c5c38cd473d0b37ad4badccde4775bb88ce34611')
def test_sparc64(self):
+ self.set_machine('sun4u')
self.root='sda'
self.wait_for_shutdown=False
self.common_tuxrun(kernel_asset=self.ASSET_SPARC64_KERNEL,
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 02/27] tests/functional/test_mips_malta: Re-enable the check for the PCI host bridge
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
2025-05-28 10:04 ` [PULL 01/27] tests/functional/test_sparc64_tuxrun: Explicitly set the 'sun4u' machine Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 03/27] tests/functional/test_mem_addr_space: Use set_machine() to select the machine Thomas Huth
` (25 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Stefan Hajnoczi, Alex Bennée, Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
The problem with the PCI bridge has been fixed in commit e5894fd6f411c1
("hw/pci-host/gt64120: Fix endianness handling"), so we can enable the
corresponding test again.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250522080208.205489-1-thuth@redhat.com>
---
tests/functional/test_mips_malta.py | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/tests/functional/test_mips_malta.py b/tests/functional/test_mips_malta.py
index 89b9556f30d..30279f0ff21 100755
--- a/tests/functional/test_mips_malta.py
+++ b/tests/functional/test_mips_malta.py
@@ -80,10 +80,8 @@ def mips_check_wheezy(test, kernel_path, image_path, kernel_command_line,
exec_command_and_wait_for_pattern(test, 'cat /proc/devices', 'usb')
exec_command_and_wait_for_pattern(test, 'cat /proc/ioports',
' : piix4_smbus')
- # lspci for the host bridge does not work on big endian targets:
- # https://gitlab.com/qemu-project/qemu/-/issues/2826
- # exec_command_and_wait_for_pattern(test, 'lspci -d 11ab:4620',
- # 'GT-64120')
+ exec_command_and_wait_for_pattern(test, 'lspci -d 11ab:4620',
+ 'GT-64120')
exec_command_and_wait_for_pattern(test,
'cat /sys/bus/i2c/devices/i2c-0/name',
'SMBus PIIX4 adapter')
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 03/27] tests/functional/test_mem_addr_space: Use set_machine() to select the machine
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
2025-05-28 10:04 ` [PULL 01/27] tests/functional/test_sparc64_tuxrun: Explicitly set the 'sun4u' machine Thomas Huth
2025-05-28 10:04 ` [PULL 02/27] tests/functional/test_mips_malta: Re-enable the check for the PCI host bridge Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 04/27] tests/functional: add skipLockedMemoryTest decorator Thomas Huth
` (24 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé, Richard Henderson
From: Thomas Huth <thuth@redhat.com>
By using self.set_machine() the tests get properly skipped in case
the machine has not been compiled into the QEMU binary, e.g. when
"configure" has been run with "--without-default-devices".
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250521143732.140711-1-thuth@redhat.com>
---
tests/functional/test_mem_addr_space.py | 63 +++++++++++++------------
1 file changed, 32 insertions(+), 31 deletions(-)
diff --git a/tests/functional/test_mem_addr_space.py b/tests/functional/test_mem_addr_space.py
index 2d9d31efb59..61b4a190b41 100755
--- a/tests/functional/test_mem_addr_space.py
+++ b/tests/functional/test_mem_addr_space.py
@@ -58,8 +58,8 @@ def test_phybits_low_pse36(self):
should start fine.
"""
self.ensure_64bit_binary()
- self.vm.add_args('-S', '-machine', 'q35', '-m',
- '512,slots=1,maxmem=59.6G',
+ self.set_machine('q35')
+ self.vm.add_args('-S', '-m', '512,slots=1,maxmem=59.6G',
'-cpu', 'pentium,pse36=on', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -76,8 +76,8 @@ def test_phybits_low_pae(self):
with pse36 above.
"""
self.ensure_64bit_binary()
- self.vm.add_args('-S', '-machine', 'q35', '-m',
- '512,slots=1,maxmem=59.6G',
+ self.set_machine('q35')
+ self.vm.add_args('-S', '-m', '512,slots=1,maxmem=59.6G',
'-cpu', 'pentium,pae=on', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -93,8 +93,8 @@ def test_phybits_ok_pentium_pse36(self):
same options as the failing case above with pse36 cpu feature.
"""
self.ensure_64bit_binary()
- self.vm.add_args('-machine', 'q35', '-m',
- '512,slots=1,maxmem=59.5G',
+ self.set_machine('q35')
+ self.vm.add_args('-m', '512,slots=1,maxmem=59.5G',
'-cpu', 'pentium,pse36=on', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -111,8 +111,8 @@ def test_phybits_ok_pentium_pae(self):
with the same options as the case above.
"""
self.ensure_64bit_binary()
- self.vm.add_args('-machine', 'q35', '-m',
- '512,slots=1,maxmem=59.5G',
+ self.set_machine('q35')
+ self.vm.add_args('-m', '512,slots=1,maxmem=59.5G',
'-cpu', 'pentium,pae=on', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -128,8 +128,8 @@ def test_phybits_ok_pentium2(self):
with pse36 ON.
"""
self.ensure_64bit_binary()
- self.vm.add_args('-machine', 'q35', '-m',
- '512,slots=1,maxmem=59.5G',
+ self.set_machine('q35')
+ self.vm.add_args('-m', '512,slots=1,maxmem=59.5G',
'-cpu', 'pentium2', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -148,8 +148,8 @@ def test_phybits_low_nonpse36(self):
above 4 GiB due to the PCI hole and simplicity.
"""
self.ensure_64bit_binary()
- self.vm.add_args('-S', '-machine', 'q35', '-m',
- '512,slots=1,maxmem=4G',
+ self.set_machine('q35')
+ self.vm.add_args('-S', '-m', '512,slots=1,maxmem=4G',
'-cpu', 'pentium', '-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -176,8 +176,8 @@ def test_phybits_low_tcg_q35_70_amd(self):
make QEMU fail with the error message.
"""
self.ensure_64bit_binary()
- self.vm.add_args('-S', '-machine', 'pc-q35-7.0', '-m',
- '512,slots=1,maxmem=988G',
+ self.set_machine('pc-q35-7.0')
+ self.vm.add_args('-S', '-m', '512,slots=1,maxmem=988G',
'-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -197,8 +197,8 @@ def test_phybits_low_tcg_q35_71_amd(self):
than 988 GiB).
"""
self.ensure_64bit_binary()
- self.vm.add_args('-S', '-machine', 'pc-q35-7.1', '-m',
- '512,slots=1,maxmem=976G',
+ self.set_machine('pc-q35-7.1')
+ self.vm.add_args('-S', '-m', '512,slots=1,maxmem=976G',
'-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -214,8 +214,8 @@ def test_phybits_ok_tcg_q35_70_amd(self):
successfully start when maxmem is < 988G.
"""
self.ensure_64bit_binary()
- self.vm.add_args('-S', '-machine', 'pc-q35-7.0', '-m',
- '512,slots=1,maxmem=987.5G',
+ self.set_machine('pc-q35-7.0')
+ self.vm.add_args('-S', '-m', '512,slots=1,maxmem=987.5G',
'-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -231,8 +231,8 @@ def test_phybits_ok_tcg_q35_71_amd(self):
successfully start when maxmem is < 976G.
"""
self.ensure_64bit_binary()
- self.vm.add_args('-S', '-machine', 'pc-q35-7.1', '-m',
- '512,slots=1,maxmem=975.5G',
+ self.set_machine('pc-q35-7.1')
+ self.vm.add_args('-S', '-m', '512,slots=1,maxmem=975.5G',
'-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -249,9 +249,9 @@ def test_phybits_ok_tcg_q35_71_intel(self):
"above_4G" memory starts at 4G.
"""
self.ensure_64bit_binary()
+ self.set_machine('pc-q35-7.1')
self.vm.add_args('-S', '-cpu', 'Skylake-Server',
- '-machine', 'pc-q35-7.1', '-m',
- '512,slots=1,maxmem=976G',
+ '-m', '512,slots=1,maxmem=976G',
'-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -274,9 +274,9 @@ def test_phybits_low_tcg_q35_71_amd_41bits(self):
fail to start.
"""
self.ensure_64bit_binary()
+ self.set_machine('pc-q35-7.1')
self.vm.add_args('-S', '-cpu', 'EPYC-v4,phys-bits=41',
- '-machine', 'pc-q35-7.1', '-m',
- '512,slots=1,maxmem=992G',
+ '-m', '512,slots=1,maxmem=992G',
'-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -293,9 +293,9 @@ def test_phybits_ok_tcg_q35_71_amd_41bits(self):
QEMU should start fine.
"""
self.ensure_64bit_binary()
+ self.set_machine('pc-q35-7.1')
self.vm.add_args('-S', '-cpu', 'EPYC-v4,phys-bits=41',
- '-machine', 'pc-q35-7.1', '-m',
- '512,slots=1,maxmem=990G',
+ '-m', '512,slots=1,maxmem=990G',
'-display', 'none',
'-object', 'memory-backend-ram,id=mem1,size=1G',
'-device', 'pc-dimm,id=vm0,memdev=mem1')
@@ -314,12 +314,12 @@ def test_phybits_low_tcg_q35_intel_cxl(self):
alignment constraints with 40 bits (1 TiB) of processor physical bits.
"""
self.ensure_64bit_binary()
+ self.set_machine('q35')
self.vm.add_args('-S', '-cpu', 'Skylake-Server,phys-bits=40',
- '-machine', 'q35,cxl=on', '-m',
- '512,slots=1,maxmem=987G',
+ '-m', '512,slots=1,maxmem=987G',
'-display', 'none',
'-device', 'pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1',
- '-M', 'cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=1G')
+ '-M', 'cxl=on,cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=1G')
self.vm.set_qmp_monitor(enabled=False)
self.vm.launch()
self.vm.wait()
@@ -333,9 +333,10 @@ def test_phybits_ok_tcg_q35_intel_cxl(self):
with cxl enabled.
"""
self.ensure_64bit_binary()
+ self.set_machine('q35')
self.vm.add_args('-S', '-cpu', 'Skylake-Server,phys-bits=40',
- '-machine', 'q35,cxl=on', '-m',
- '512,slots=1,maxmem=987G',
+ '-machine', 'cxl=on',
+ '-m', '512,slots=1,maxmem=987G',
'-display', 'none',
'-device', 'pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1')
self.vm.set_qmp_monitor(enabled=False)
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 04/27] tests/functional: add skipLockedMemoryTest decorator
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (2 preceding siblings ...)
2025-05-28 10:04 ` [PULL 03/27] tests/functional/test_mem_addr_space: Use set_machine() to select the machine Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 05/27] tests/functional: add memlock tests Thomas Huth
` (23 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Stefan Hajnoczi, Alexandr Moshkov
From: Alexandr Moshkov <dtalexundeer@yandex-team.ru>
Used in future commit to skipping execution of a tests if the system's
locked memory limit is below the required threshold.
Signed-off-by: Alexandr Moshkov <dtalexundeer@yandex-team.ru>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250525070737.54267-2-dtalexundeer@yandex-team.ru>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
tests/functional/qemu_test/__init__.py | 2 +-
tests/functional/qemu_test/decorators.py | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/tests/functional/qemu_test/__init__.py b/tests/functional/qemu_test/__init__.py
index af41c2c6a22..6e666a059fc 100644
--- a/tests/functional/qemu_test/__init__.py
+++ b/tests/functional/qemu_test/__init__.py
@@ -15,6 +15,6 @@
from .linuxkernel import LinuxKernelTest
from .decorators import skipIfMissingCommands, skipIfNotMachine, \
skipFlakyTest, skipUntrustedTest, skipBigDataTest, skipSlowTest, \
- skipIfMissingImports, skipIfOperatingSystem
+ skipIfMissingImports, skipIfOperatingSystem, skipLockedMemoryTest
from .archive import archive_extract
from .uncompress import uncompress
diff --git a/tests/functional/qemu_test/decorators.py b/tests/functional/qemu_test/decorators.py
index 50d29de533d..c0d1567b142 100644
--- a/tests/functional/qemu_test/decorators.py
+++ b/tests/functional/qemu_test/decorators.py
@@ -5,6 +5,7 @@
import importlib
import os
import platform
+import resource
from unittest import skipIf, skipUnless
from .cmd import which
@@ -131,3 +132,20 @@ def skipIfMissingImports(*args):
return skipUnless(has_imports, 'required import(s) "%s" not installed' %
", ".join(args))
+
+'''
+Decorator to skip execution of a test if the system's
+locked memory limit is below the required threshold.
+Takes required locked memory threshold in kB.
+Example:
+
+ @skipLockedMemoryTest(2_097_152)
+'''
+def skipLockedMemoryTest(locked_memory):
+ # get memlock hard limit in bytes
+ _, ulimit_memory = resource.getrlimit(resource.RLIMIT_MEMLOCK)
+
+ return skipUnless(
+ ulimit_memory == resource.RLIM_INFINITY or ulimit_memory >= locked_memory * 1024,
+ f'Test required {locked_memory} kB of available locked memory',
+ )
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 05/27] tests/functional: add memlock tests
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (3 preceding siblings ...)
2025-05-28 10:04 ` [PULL 04/27] tests/functional: add skipLockedMemoryTest decorator Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 06/27] hw/microblaze: Add endianness property to the petalogix_s3adsp1800 machine Thomas Huth
` (22 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Stefan Hajnoczi, Alexandr Moshkov
From: Alexandr Moshkov <dtalexundeer@yandex-team.ru>
Add new tests to check the correctness of the `-overcommit memlock`
option (possible values: off, on, on-fault) by using
`/proc/{qemu_pid}/status` file to check in VmSize, VmRSS and VmLck
values:
* if `memlock=off`, then VmLck = 0;
* if `memlock=on`, then VmLck > 0 and almost all memory is resident;
* if `memlock=on-fault`, then VmLck > 0 and only few memory is resident.
Signed-off-by: Alexandr Moshkov <dtalexundeer@yandex-team.ru>
Message-ID: <20250525070737.54267-3-dtalexundeer@yandex-team.ru>
[thuth: improved the text in a comment]
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
tests/functional/meson.build | 1 +
tests/functional/test_memlock.py | 79 ++++++++++++++++++++++++++++++++
2 files changed, 80 insertions(+)
create mode 100755 tests/functional/test_memlock.py
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index 52b4706cfe8..13079f58b66 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -68,6 +68,7 @@ tests_generic_system = [
'empty_cpu_model',
'info_usernet',
'version',
+ 'memlock',
]
tests_generic_linuxuser = [
diff --git a/tests/functional/test_memlock.py b/tests/functional/test_memlock.py
new file mode 100755
index 00000000000..8910cb6da33
--- /dev/null
+++ b/tests/functional/test_memlock.py
@@ -0,0 +1,79 @@
+#!/usr/bin/env python3
+#
+# Functional test that check overcommit memlock options
+#
+# Copyright (c) Yandex Technologies LLC, 2025
+#
+# Author:
+# Alexandr Moshkov <dtalexundeer@yandex-team.ru>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import re
+
+from typing import Dict
+
+from qemu_test import QemuSystemTest
+from qemu_test import skipLockedMemoryTest
+
+
+STATUS_VALUE_PATTERN = re.compile(r'^(\w+):\s+(\d+) kB', re.MULTILINE)
+
+
+@skipLockedMemoryTest(2_097_152) # 2GB
+class MemlockTest(QemuSystemTest):
+ """
+ Runs a guest with memlock options.
+ Then verify, that this options is working correctly
+ by checking the smaps of the QEMU process.
+ """
+
+ def common_vm_setup_with_memlock(self, memlock):
+ self.vm.add_args('-overcommit', f'mem-lock={memlock}')
+ self.vm.launch()
+
+ def test_memlock_off(self):
+ self.common_vm_setup_with_memlock('off')
+
+ status = self.get_process_status_values(self.vm.get_pid())
+
+ self.assertTrue(status['VmLck'] == 0)
+
+ def test_memlock_on(self):
+ self.common_vm_setup_with_memlock('on')
+
+ status = self.get_process_status_values(self.vm.get_pid())
+
+ # VmLck > 0 kB and almost all memory is resident
+ self.assertTrue(status['VmLck'] > 0)
+ self.assertTrue(status['VmRSS'] >= status['VmSize'] * 0.70)
+
+ def test_memlock_onfault(self):
+ self.common_vm_setup_with_memlock('on-fault')
+
+ status = self.get_process_status_values(self.vm.get_pid())
+
+ # VmLck > 0 kB and only few memory is resident
+ self.assertTrue(status['VmLck'] > 0)
+ self.assertTrue(status['VmRSS'] <= status['VmSize'] * 0.30)
+
+ def get_process_status_values(self, pid: int) -> Dict[str, int]:
+ result = {}
+ raw_status = self._get_raw_process_status(pid)
+
+ for line in raw_status.split('\n'):
+ if m := STATUS_VALUE_PATTERN.match(line):
+ result[m.group(1)] = int(m.group(2))
+
+ return result
+
+ def _get_raw_process_status(self, pid: int) -> str:
+ try:
+ with open(f'/proc/{pid}/status', 'r') as f:
+ return f.read()
+ except FileNotFoundError:
+ self.skipTest("Can't open status file of the process")
+
+
+if __name__ == '__main__':
+ MemlockTest.main()
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 06/27] hw/microblaze: Add endianness property to the petalogix_s3adsp1800 machine
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (4 preceding siblings ...)
2025-05-28 10:04 ` [PULL 05/27] tests/functional: add memlock tests Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 07/27] tests/functional: Test both microblaze s3adsp1800 endianness variants Thomas Huth
` (21 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
Since the microblaze target can now handle both endianness, big and
little, we should provide a config knob for the user to select the
desired endianness.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250515132019.569365-2-thuth@redhat.com>
---
hw/microblaze/petalogix_s3adsp1800_mmu.c | 41 +++++++++++++++++++++---
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
index 032f6f70eac..edc5d0dcfd0 100644
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
@@ -58,9 +58,20 @@
#define TYPE_PETALOGIX_S3ADSP1800_MACHINE \
MACHINE_TYPE_NAME("petalogix-s3adsp1800")
+struct S3Adsp1800MachineState {
+ MachineState parent_class;
+
+ EndianMode endianness;
+};
+
+OBJECT_DECLARE_TYPE(S3Adsp1800MachineState, MachineClass,
+ PETALOGIX_S3ADSP1800_MACHINE)
+
+
static void
petalogix_s3adsp1800_init(MachineState *machine)
{
+ S3Adsp1800MachineState *psms = PETALOGIX_S3ADSP1800_MACHINE(machine);
ram_addr_t ram_size = machine->ram_size;
DeviceState *dev;
MicroBlazeCPU *cpu;
@@ -71,13 +82,12 @@ petalogix_s3adsp1800_init(MachineState *machine)
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
MemoryRegion *sysmem = get_system_memory();
- EndianMode endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG
- : ENDIAN_MODE_LITTLE;
+ EndianMode endianness = psms->endianness;
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort);
object_property_set_bool(OBJECT(cpu), "little-endian",
- !TARGET_BIG_ENDIAN, &error_abort);
+ endianness == ENDIAN_MODE_LITTLE, &error_abort);
qdev_realize(DEVICE(cpu), NULL, &error_abort);
/* Attach emulated BRAM through the LMB. */
@@ -135,20 +145,41 @@ petalogix_s3adsp1800_init(MachineState *machine)
create_unimplemented_device("xps_gpio", GPIO_BASEADDR, 0x10000);
- microblaze_load_kernel(cpu, !TARGET_BIG_ENDIAN, ddr_base, ram_size,
- machine->initrd_filename,
+ microblaze_load_kernel(cpu, endianness == ENDIAN_MODE_LITTLE, ddr_base,
+ ram_size, machine->initrd_filename,
BINARY_DEVICE_TREE_FILE,
NULL);
}
+static int machine_get_endianness(Object *obj, Error **errp G_GNUC_UNUSED)
+{
+ S3Adsp1800MachineState *ms = PETALOGIX_S3ADSP1800_MACHINE(obj);
+ return ms->endianness;
+}
+
+static void machine_set_endianness(Object *obj, int endianness, Error **errp)
+{
+ S3Adsp1800MachineState *ms = PETALOGIX_S3ADSP1800_MACHINE(obj);
+ ms->endianness = endianness;
+}
+
static void petalogix_s3adsp1800_machine_class_init(ObjectClass *oc,
const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ ObjectProperty *prop;
mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800";
mc->init = petalogix_s3adsp1800_init;
mc->is_default = true;
+
+ prop = object_class_property_add_enum(oc, "endianness", "EndianMode",
+ &EndianMode_lookup,
+ machine_get_endianness,
+ machine_set_endianness);
+ object_property_set_default_str(prop, TARGET_BIG_ENDIAN ? "big" : "little");
+ object_class_property_set_description(oc, "endianness",
+ "Defines whether the machine runs in big or little endian mode");
}
static const TypeInfo petalogix_s3adsp1800_machine_types[] = {
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 07/27] tests/functional: Test both microblaze s3adsp1800 endianness variants
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (5 preceding siblings ...)
2025-05-28 10:04 ` [PULL 06/27] hw/microblaze: Add endianness property to the petalogix_s3adsp1800 machine Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 08/27] hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu Thomas Huth
` (20 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
Now that the endianness of the petalogix-s3adsp1800 can be configured,
we should test that the cross-endianness also works as expected, thus
test the big endian variant on the little endian target and vice versa.
(based on an original idea from Philippe Mathieu-Daudé)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250515132019.569365-3-thuth@redhat.com>
---
tests/functional/test_microblaze_s3adsp1800.py | 18 +++++++++++++-----
.../functional/test_microblazeel_s3adsp1800.py | 6 +++++-
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/tests/functional/test_microblaze_s3adsp1800.py b/tests/functional/test_microblaze_s3adsp1800.py
index c93fa14232b..f093b162c0a 100755
--- a/tests/functional/test_microblaze_s3adsp1800.py
+++ b/tests/functional/test_microblaze_s3adsp1800.py
@@ -25,12 +25,14 @@ class MicroblazeMachine(QemuSystemTest):
('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'),
'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
- def do_ballerina_be_test(self, machine):
- self.set_machine(machine)
+ def do_ballerina_be_test(self, force_endianness=False):
+ self.set_machine('petalogix-s3adsp1800')
self.archive_extract(self.ASSET_IMAGE_BE)
self.vm.set_console()
self.vm.add_args('-kernel',
self.scratch_file('day17', 'ballerina.bin'))
+ if force_endianness:
+ self.vm.add_args('-M', 'endianness=big')
self.vm.launch()
wait_for_console_pattern(self, 'This architecture does not have '
'kernel memory protection')
@@ -39,12 +41,14 @@ def do_ballerina_be_test(self, machine):
# message, that's why we don't test for a later string here. This
# needs some investigation by a microblaze wizard one day...
- def do_xmaton_le_test(self, machine):
+ def do_xmaton_le_test(self, force_endianness=False):
self.require_netdev('user')
- self.set_machine(machine)
+ self.set_machine('petalogix-s3adsp1800')
self.archive_extract(self.ASSET_IMAGE_LE)
self.vm.set_console()
self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin'))
+ if force_endianness:
+ self.vm.add_args('-M', 'endianness=little')
tftproot = self.scratch_file('day13')
self.vm.add_args('-nic', f'user,tftp={tftproot}')
self.vm.launch()
@@ -59,9 +63,13 @@ def do_xmaton_le_test(self, machine):
class MicroblazeBigEndianMachine(MicroblazeMachine):
ASSET_IMAGE_BE = MicroblazeMachine.ASSET_IMAGE_BE
+ ASSET_IMAGE_LE = MicroblazeMachine.ASSET_IMAGE_LE
def test_microblaze_s3adsp1800_legacy_be(self):
- self.do_ballerina_be_test('petalogix-s3adsp1800')
+ self.do_ballerina_be_test()
+
+ def test_microblaze_s3adsp1800_legacy_le(self):
+ self.do_xmaton_le_test(force_endianness=True)
if __name__ == '__main__':
diff --git a/tests/functional/test_microblazeel_s3adsp1800.py b/tests/functional/test_microblazeel_s3adsp1800.py
index ab59941d57a..915902d48bd 100755
--- a/tests/functional/test_microblazeel_s3adsp1800.py
+++ b/tests/functional/test_microblazeel_s3adsp1800.py
@@ -13,9 +13,13 @@
class MicroblazeLittleEndianMachine(MicroblazeMachine):
ASSET_IMAGE_LE = MicroblazeMachine.ASSET_IMAGE_LE
+ ASSET_IMAGE_BE = MicroblazeMachine.ASSET_IMAGE_BE
def test_microblaze_s3adsp1800_legacy_le(self):
- self.do_xmaton_le_test('petalogix-s3adsp1800')
+ self.do_xmaton_le_test()
+
+ def test_microblaze_s3adsp1800_legacy_be(self):
+ self.do_ballerina_be_test(force_endianness=True)
if __name__ == '__main__':
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 08/27] hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (6 preceding siblings ...)
2025-05-28 10:04 ` [PULL 07/27] tests/functional: Test both microblaze s3adsp1800 endianness variants Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 09/27] docs: Deprecate the qemu-system-microblazeel binary Thomas Huth
` (19 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Richard Henderson, Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
Both machines were added with little-endian in mind only (the
"endianness" CPU property was hard-wired to "true", see commits
133d23b3ad1 and a88bbb006a52), so the variants that showed up
on the big endian target likely never worked. We deprecated these
non-working machine variants two releases ago, and so far nobody
complained, so it should be fine now to disable them. Hard-wire
the machines to little endian now.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250515132019.569365-4-thuth@redhat.com>
---
docs/about/deprecated.rst | 6 ------
docs/about/removed-features.rst | 9 +++++++++
hw/microblaze/petalogix_ml605_mmu.c | 15 ++++-----------
hw/microblaze/xlnx-zynqmp-pmu.c | 7 +------
4 files changed, 14 insertions(+), 23 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 44d3427e989..f3bf02d8b88 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -324,12 +324,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name
better reflects the way this property affects all random data within
the device tree blob, not just the ``kaslr-seed`` node.
-Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2)
-''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
-
-Both ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` were added for little endian
-CPUs. Big endian support is not tested.
-
Mips ``mipssim`` machine (since 10.0)
'''''''''''''''''''''''''''''''''''''
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index 063284d4f8a..9df5aba0bb6 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -1082,6 +1082,15 @@ This machine was removed because PPC 405 CPU have no known users,
firmware images are not available, OpenWRT dropped support in 2019,
U-Boot in 2017, and Linux in 2024.
+Big-Endian variants of ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (removed in 10.1)
+'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+Both the MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines
+were added for little endian CPUs. Big endian support was never tested
+and likely never worked. Starting with QEMU v10.1, the machines are now
+only available as little-endian machines.
+
+
linux-user mode CPUs
--------------------
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index bea6b689fd1..6e923c49cfc 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -80,8 +80,6 @@ petalogix_ml605_init(MachineState *machine)
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
- EndianMode endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG
- : ENDIAN_MODE_LITTLE;
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
@@ -113,7 +111,7 @@ petalogix_ml605_init(MachineState *machine)
dev = qdev_new("xlnx.xps-intc");
- qdev_prop_set_enum(dev, "endianness", endianness);
+ qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
@@ -129,7 +127,7 @@ petalogix_ml605_init(MachineState *machine)
/* 2 timers at irq 2 @ 100 Mhz. */
dev = qdev_new("xlnx.xps-timer");
- qdev_prop_set_enum(dev, "endianness", endianness);
+ qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@@ -177,7 +175,7 @@ petalogix_ml605_init(MachineState *machine)
SSIBus *spi;
dev = qdev_new("xlnx.xps-spi");
- qdev_prop_set_enum(dev, "endianness", endianness);
+ qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
@@ -218,12 +216,7 @@ petalogix_ml605_init(MachineState *machine)
static void petalogix_ml605_machine_init(MachineClass *mc)
{
- if (TARGET_BIG_ENDIAN) {
- mc->desc = "PetaLogix linux refdesign for xilinx ml605 (big endian)";
- mc->deprecation_reason = "big endian support is not tested";
- } else {
- mc->desc = "PetaLogix linux refdesign for xilinx ml605 (little endian)";
- }
+ mc->desc = "PetaLogix linux refdesign for xilinx ml605 (little endian)";
mc->init = petalogix_ml605_init;
}
diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
index ed40b5f2e05..e909802bb74 100644
--- a/hw/microblaze/xlnx-zynqmp-pmu.c
+++ b/hw/microblaze/xlnx-zynqmp-pmu.c
@@ -181,12 +181,7 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
{
- if (TARGET_BIG_ENDIAN) {
- mc->desc = "Xilinx ZynqMP PMU machine (big endian)";
- mc->deprecation_reason = "big endian support is not tested";
- } else {
- mc->desc = "Xilinx ZynqMP PMU machine (little endian)";
- }
+ mc->desc = "Xilinx ZynqMP PMU machine (little endian)";
mc->init = xlnx_zynqmp_pmu_init;
}
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 09/27] docs: Deprecate the qemu-system-microblazeel binary
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (7 preceding siblings ...)
2025-05-28 10:04 ` [PULL 08/27] hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 10/27] hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines Thomas Huth
` (18 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Richard Henderson, Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
The (former big-endian only) binary qemu-system-microblaze can
handle both endiannesses nowadays, so we don't need the separate
qemu-system-microblazeel binary for little endian anymore. Let's
deprecate it to avoid unnecessary compilation and test time in
the future.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20250515132019.569365-5-thuth@redhat.com>
---
docs/about/deprecated.rst | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index f3bf02d8b88..891f8dedc90 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -354,6 +354,19 @@ machine must ensure that they're setting the ``spike`` machine in the
command line (``-M spike``).
+System emulator binaries
+------------------------
+
+``qemu-system-microblazeel`` (since 10.1)
+'''''''''''''''''''''''''''''''''''''''''
+
+The ``qemu-system-microblaze`` binary can emulate little-endian machines
+now, too, so the separate binary ``qemu-system-microblazeel`` (with the
+``el`` suffix) for little-endian targets is not required anymore. The
+``petalogix-s3adsp1800`` machine can now be switched to little endian by
+setting its ``endianness`` property to ``little``.
+
+
Backend options
---------------
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 10/27] hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (8 preceding siblings ...)
2025-05-28 10:04 ` [PULL 09/27] docs: Deprecate the qemu-system-microblazeel binary Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 11/27] hw/i386/pc: Remove PCMachineClass::broken_reserved_end field Thomas Huth
` (17 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Remove the qtest in test-x86-cpuid-compat.c file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-2-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
hw/i386/pc_piix.c | 13 -------------
hw/i386/pc_q35.c | 13 -------------
tests/qtest/test-x86-cpuid-compat.c | 14 --------------
3 files changed, 40 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0dce512f184..04213b45b44 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -791,19 +791,6 @@ static void pc_i440fx_machine_2_5_options(MachineClass *m)
DEFINE_I440FX_MACHINE(2, 5);
-static void pc_i440fx_machine_2_4_options(MachineClass *m)
-{
- PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
-
- pc_i440fx_machine_2_5_options(m);
- m->hw_version = "2.4.0";
- pcmc->broken_reserved_end = true;
- compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
- compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
-}
-
-DEFINE_I440FX_MACHINE(2, 4);
-
#ifdef CONFIG_ISAPC
static void isapc_machine_options(MachineClass *m)
{
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index c538b3d05b4..47e12602413 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -685,16 +685,3 @@ static void pc_q35_machine_2_5_options(MachineClass *m)
}
DEFINE_Q35_MACHINE(2, 5);
-
-static void pc_q35_machine_2_4_options(MachineClass *m)
-{
- PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
-
- pc_q35_machine_2_5_options(m);
- m->hw_version = "2.4.0";
- pcmc->broken_reserved_end = true;
- compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
- compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
-}
-
-DEFINE_Q35_MACHINE(2, 4);
diff --git a/tests/qtest/test-x86-cpuid-compat.c b/tests/qtest/test-x86-cpuid-compat.c
index c9de47bb269..456e2af6657 100644
--- a/tests/qtest/test-x86-cpuid-compat.c
+++ b/tests/qtest/test-x86-cpuid-compat.c
@@ -365,20 +365,6 @@ int main(int argc, char **argv)
"level", 10);
}
- /*
- * xlevel doesn't have any feature that triggers auto-level
- * code on old machine-types. Just check that the compat code
- * is working correctly:
- */
- if (qtest_has_machine("pc-i440fx-2.4")) {
- add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.4/npt-off",
- "SandyBridge", NULL, "pc-i440fx-2.4",
- "xlevel", 0x80000008);
- add_cpuid_test("x86/cpuid/xlevel-compat/pc-i440fx-2.4/npt-on",
- "SandyBridge", "svm=on,npt=on", "pc-i440fx-2.4",
- "xlevel", 0x80000008);
- }
-
/* Test feature parsing */
add_feature_test("x86/cpuid/features/plus",
"486", "+arat",
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 11/27] hw/i386/pc: Remove PCMachineClass::broken_reserved_end field
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (9 preceding siblings ...)
2025-05-28 10:04 ` [PULL 10/27] hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 12/27] hw/i386/pc: Remove pc_compat_2_4[] array Thomas Huth
` (16 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The PCMachineClass::broken_reserved_end field was only used
by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed.
Remove it and simplify pc_memory_init().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-3-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 13 +++++--------
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 9563674e2da..f4a874b17fc 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -107,7 +107,6 @@ struct PCMachineClass {
/* RAM / address space compat: */
bool gigabyte_align;
bool has_reserved_memory;
- bool broken_reserved_end;
bool enforce_amd_1tb_hole;
bool isa_bios_alias;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 70656157ca0..c8bb4a3ee47 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -999,14 +999,13 @@ void pc_memory_init(PCMachineState *pcms,
if (machine->device_memory) {
uint64_t *val = g_malloc(sizeof(*val));
- uint64_t res_mem_end = machine->device_memory->base;
-
- if (!pcmc->broken_reserved_end) {
- res_mem_end += memory_region_size(&machine->device_memory->mr);
- }
+ uint64_t res_mem_end;
if (pcms->cxl_devices_state.is_enabled) {
res_mem_end = cxl_resv_end;
+ } else {
+ res_mem_end = machine->device_memory->base
+ + memory_region_size(&machine->device_memory->mr);
}
*val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
@@ -1044,9 +1043,7 @@ uint64_t pc_pci_hole64_start(void)
hole64_start = pc_get_cxl_range_end(pcms);
} else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
pc_get_device_memory_range(pcms, &hole64_start, &size);
- if (!pcmc->broken_reserved_end) {
- hole64_start += size;
- }
+ hole64_start += size;
} else {
hole64_start = pc_above_4g_end(pcms);
}
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 12/27] hw/i386/pc: Remove pc_compat_2_4[] array
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (10 preceding siblings ...)
2025-05-28 10:04 ` [PULL 11/27] hw/i386/pc: Remove PCMachineClass::broken_reserved_end field Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 13/27] hw/core/machine: Remove hw_compat_2_4[] array Thomas Huth
` (15 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The pc_compat_2_4[] array was only used by the pc-q35-2.4
and pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-4-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
include/hw/i386/pc.h | 3 ---
hw/i386/pc.c | 19 -------------------
2 files changed, 22 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index f4a874b17fc..b34aa25fdce 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -301,9 +301,6 @@ extern const size_t pc_compat_2_6_len;
extern GlobalProperty pc_compat_2_5[];
extern const size_t pc_compat_2_5_len;
-extern GlobalProperty pc_compat_2_4[];
-extern const size_t pc_compat_2_4_len;
-
#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
static void pc_machine_##suffix##_class_init(ObjectClass *oc, \
const void *data) \
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index c8bb4a3ee47..2b46714a5ac 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -262,25 +262,6 @@ const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
GlobalProperty pc_compat_2_5[] = {};
const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
-GlobalProperty pc_compat_2_4[] = {
- PC_CPU_MODEL_IDS("2.4.0")
- { "Haswell-" TYPE_X86_CPU, "abm", "off" },
- { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
- { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
- { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
- { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
- { TYPE_X86_CPU, "check", "off" },
- { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
- { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
- { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
- { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
- { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
- { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
- { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
- { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
-};
-const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
-
/*
* @PC_FW_DATA:
* Size of the chunk of memory at the top of RAM for the BIOS ACPI tables
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 13/27] hw/core/machine: Remove hw_compat_2_4[] array
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (11 preceding siblings ...)
2025-05-28 10:04 ` [PULL 12/27] hw/i386/pc: Remove pc_compat_2_4[] array Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 14/27] hw/net/e1000: Remove unused E1000_FLAG_MAC flag Thomas Huth
` (14 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The hw_compat_2_4[] array was only used by the pc-q35-2.4 and
pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-6-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
include/hw/boards.h | 3 ---
hw/core/machine.c | 9 ---------
2 files changed, 12 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index a7b1fcffae3..03e7cbeae82 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -866,7 +866,4 @@ extern const size_t hw_compat_2_6_len;
extern GlobalProperty hw_compat_2_5[];
extern const size_t hw_compat_2_5_len;
-extern GlobalProperty hw_compat_2_4[];
-extern const size_t hw_compat_2_4_len;
-
#endif
diff --git a/hw/core/machine.c b/hw/core/machine.c
index c3f3a5020d0..15cd2bc3c40 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -294,15 +294,6 @@ GlobalProperty hw_compat_2_5[] = {
};
const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
-GlobalProperty hw_compat_2_4[] = {
- { "e1000", "extra_mac_registers", "off" },
- { "virtio-pci", "x-disable-pcie", "on" },
- { "virtio-pci", "migrate-extra", "off" },
- { "fw_cfg_mem", "dma_enabled", "off" },
- { "fw_cfg_io", "dma_enabled", "off" }
-};
-const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
-
MachineState *current_machine;
static char *machine_get_kernel(Object *obj, Error **errp)
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 14/27] hw/net/e1000: Remove unused E1000_FLAG_MAC flag
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (12 preceding siblings ...)
2025-05-28 10:04 ` [PULL 13/27] hw/core/machine: Remove hw_compat_2_4[] array Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 15/27] hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition Thomas Huth
` (13 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu
From: Philippe Mathieu-Daudé <philmd@linaro.org>
E1000_FLAG_MAC was only used by the hw_compat_2_4[] array,
via the 'extra_mac_registers=off' property. We removed all
machines using that array, lets remove all the code around
E1000_FLAG_MAC, including the MAC_ACCESS_FLAG_NEEDED enum,
similarly to commit fa4ec9ffda7 ("e1000: remove old
compatibility code").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-ID: <20250512083948.39294-7-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
hw/net/e1000.c | 95 ++++++++++++++++++++++----------------------------
1 file changed, 41 insertions(+), 54 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index cba4999e6d0..a80a7b0cdb4 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -127,10 +127,8 @@ struct E1000State_st {
QEMUTimer *flush_queue_timer;
/* Compatibility flags for migration to/from qemu 1.3.0 and older */
-#define E1000_FLAG_MAC_BIT 2
#define E1000_FLAG_TSO_BIT 3
#define E1000_FLAG_VET_BIT 4
-#define E1000_FLAG_MAC (1 << E1000_FLAG_MAC_BIT)
#define E1000_FLAG_TSO (1 << E1000_FLAG_TSO_BIT)
#define E1000_FLAG_VET (1 << E1000_FLAG_VET_BIT)
@@ -1212,52 +1210,51 @@ enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
enum { MAC_ACCESS_PARTIAL = 1, MAC_ACCESS_FLAG_NEEDED = 2 };
-#define markflag(x) ((E1000_FLAG_##x << 2) | MAC_ACCESS_FLAG_NEEDED)
/* In the array below the meaning of the bits is: [f|f|f|f|f|f|n|p]
* f - flag bits (up to 6 possible flags)
* n - flag needed
- * p - partially implenented */
+ * p - partially implemented */
static const uint8_t mac_reg_access[0x8000] = {
- [IPAV] = markflag(MAC), [WUC] = markflag(MAC),
- [IP6AT] = markflag(MAC), [IP4AT] = markflag(MAC),
- [FFVT] = markflag(MAC), [WUPM] = markflag(MAC),
- [ECOL] = markflag(MAC), [MCC] = markflag(MAC),
- [DC] = markflag(MAC), [TNCRS] = markflag(MAC),
- [RLEC] = markflag(MAC), [XONRXC] = markflag(MAC),
- [XOFFTXC] = markflag(MAC), [RFC] = markflag(MAC),
- [TSCTFC] = markflag(MAC), [MGTPRC] = markflag(MAC),
- [WUS] = markflag(MAC), [AIT] = markflag(MAC),
- [FFLT] = markflag(MAC), [FFMT] = markflag(MAC),
- [SCC] = markflag(MAC), [FCRUC] = markflag(MAC),
- [LATECOL] = markflag(MAC), [COLC] = markflag(MAC),
- [SEQEC] = markflag(MAC), [CEXTERR] = markflag(MAC),
- [XONTXC] = markflag(MAC), [XOFFRXC] = markflag(MAC),
- [RJC] = markflag(MAC), [RNBC] = markflag(MAC),
- [MGTPDC] = markflag(MAC), [MGTPTC] = markflag(MAC),
- [RUC] = markflag(MAC), [ROC] = markflag(MAC),
- [GORCL] = markflag(MAC), [GORCH] = markflag(MAC),
- [GOTCL] = markflag(MAC), [GOTCH] = markflag(MAC),
- [BPRC] = markflag(MAC), [MPRC] = markflag(MAC),
- [TSCTC] = markflag(MAC), [PRC64] = markflag(MAC),
- [PRC127] = markflag(MAC), [PRC255] = markflag(MAC),
- [PRC511] = markflag(MAC), [PRC1023] = markflag(MAC),
- [PRC1522] = markflag(MAC), [PTC64] = markflag(MAC),
- [PTC127] = markflag(MAC), [PTC255] = markflag(MAC),
- [PTC511] = markflag(MAC), [PTC1023] = markflag(MAC),
- [PTC1522] = markflag(MAC), [MPTC] = markflag(MAC),
- [BPTC] = markflag(MAC),
-
- [TDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [TDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [TDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [TDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [TDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [RDFH] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [RDFT] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [RDFHS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [RDFTS] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [RDFPC] = markflag(MAC) | MAC_ACCESS_PARTIAL,
- [PBM] = markflag(MAC) | MAC_ACCESS_PARTIAL,
+ [IPAV] = MAC_ACCESS_FLAG_NEEDED, [WUC] = MAC_ACCESS_FLAG_NEEDED,
+ [IP6AT] = MAC_ACCESS_FLAG_NEEDED, [IP4AT] = MAC_ACCESS_FLAG_NEEDED,
+ [FFVT] = MAC_ACCESS_FLAG_NEEDED, [WUPM] = MAC_ACCESS_FLAG_NEEDED,
+ [ECOL] = MAC_ACCESS_FLAG_NEEDED, [MCC] = MAC_ACCESS_FLAG_NEEDED,
+ [DC] = MAC_ACCESS_FLAG_NEEDED, [TNCRS] = MAC_ACCESS_FLAG_NEEDED,
+ [RLEC] = MAC_ACCESS_FLAG_NEEDED, [XONRXC] = MAC_ACCESS_FLAG_NEEDED,
+ [XOFFTXC] = MAC_ACCESS_FLAG_NEEDED, [RFC] = MAC_ACCESS_FLAG_NEEDED,
+ [TSCTFC] = MAC_ACCESS_FLAG_NEEDED, [MGTPRC] = MAC_ACCESS_FLAG_NEEDED,
+ [WUS] = MAC_ACCESS_FLAG_NEEDED, [AIT] = MAC_ACCESS_FLAG_NEEDED,
+ [FFLT] = MAC_ACCESS_FLAG_NEEDED, [FFMT] = MAC_ACCESS_FLAG_NEEDED,
+ [SCC] = MAC_ACCESS_FLAG_NEEDED, [FCRUC] = MAC_ACCESS_FLAG_NEEDED,
+ [LATECOL] = MAC_ACCESS_FLAG_NEEDED, [COLC] = MAC_ACCESS_FLAG_NEEDED,
+ [SEQEC] = MAC_ACCESS_FLAG_NEEDED, [CEXTERR] = MAC_ACCESS_FLAG_NEEDED,
+ [XONTXC] = MAC_ACCESS_FLAG_NEEDED, [XOFFRXC] = MAC_ACCESS_FLAG_NEEDED,
+ [RJC] = MAC_ACCESS_FLAG_NEEDED, [RNBC] = MAC_ACCESS_FLAG_NEEDED,
+ [MGTPDC] = MAC_ACCESS_FLAG_NEEDED, [MGTPTC] = MAC_ACCESS_FLAG_NEEDED,
+ [RUC] = MAC_ACCESS_FLAG_NEEDED, [ROC] = MAC_ACCESS_FLAG_NEEDED,
+ [GORCL] = MAC_ACCESS_FLAG_NEEDED, [GORCH] = MAC_ACCESS_FLAG_NEEDED,
+ [GOTCL] = MAC_ACCESS_FLAG_NEEDED, [GOTCH] = MAC_ACCESS_FLAG_NEEDED,
+ [BPRC] = MAC_ACCESS_FLAG_NEEDED, [MPRC] = MAC_ACCESS_FLAG_NEEDED,
+ [TSCTC] = MAC_ACCESS_FLAG_NEEDED, [PRC64] = MAC_ACCESS_FLAG_NEEDED,
+ [PRC127] = MAC_ACCESS_FLAG_NEEDED, [PRC255] = MAC_ACCESS_FLAG_NEEDED,
+ [PRC511] = MAC_ACCESS_FLAG_NEEDED, [PRC1023] = MAC_ACCESS_FLAG_NEEDED,
+ [PRC1522] = MAC_ACCESS_FLAG_NEEDED, [PTC64] = MAC_ACCESS_FLAG_NEEDED,
+ [PTC127] = MAC_ACCESS_FLAG_NEEDED, [PTC255] = MAC_ACCESS_FLAG_NEEDED,
+ [PTC511] = MAC_ACCESS_FLAG_NEEDED, [PTC1023] = MAC_ACCESS_FLAG_NEEDED,
+ [PTC1522] = MAC_ACCESS_FLAG_NEEDED, [MPTC] = MAC_ACCESS_FLAG_NEEDED,
+ [BPTC] = MAC_ACCESS_FLAG_NEEDED,
+
+ [TDFH] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [TDFT] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [TDFHS] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [TDFTS] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [TDFPC] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [RDFH] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [RDFT] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [RDFHS] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [RDFTS] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [RDFPC] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
+ [PBM] = MAC_ACCESS_FLAG_NEEDED | MAC_ACCESS_PARTIAL,
};
static void
@@ -1419,13 +1416,6 @@ static int e1000_tx_tso_post_load(void *opaque, int version_id)
return 0;
}
-static bool e1000_full_mac_needed(void *opaque)
-{
- E1000State *s = opaque;
-
- return chkflag(MAC);
-}
-
static bool e1000_tso_state_needed(void *opaque)
{
E1000State *s = opaque;
@@ -1451,7 +1441,6 @@ static const VMStateDescription vmstate_e1000_full_mac_state = {
.name = "e1000/full_mac_state",
.version_id = 1,
.minimum_version_id = 1,
- .needed = e1000_full_mac_needed,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(mac_reg, E1000State, 0x8000),
VMSTATE_END_OF_LIST()
@@ -1679,8 +1668,6 @@ static void pci_e1000_realize(PCIDevice *pci_dev, Error **errp)
static const Property e1000_properties[] = {
DEFINE_NIC_PROPERTIES(E1000State, conf),
- DEFINE_PROP_BIT("extra_mac_registers", E1000State,
- compat_flags, E1000_FLAG_MAC_BIT, true),
DEFINE_PROP_BIT("migrate_tso_props", E1000State,
compat_flags, E1000_FLAG_TSO_BIT, true),
DEFINE_PROP_BIT("init-vet", E1000State,
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 15/27] hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (13 preceding siblings ...)
2025-05-28 10:04 ` [PULL 14/27] hw/net/e1000: Remove unused E1000_FLAG_MAC flag Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 16/27] hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition Thomas Huth
` (12 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu
From: Philippe Mathieu-Daudé <philmd@linaro.org>
VIRTIO_PCI_FLAG_MIGRATE_EXTRA was only used by the
hw_compat_2_4[] array, via the 'migrate-extra=true'
property. We removed all machines using that array,
lets remove all the code around VIRTIO_PCI_FLAG_MIGRATE_EXTRA.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-ID: <20250512083948.39294-8-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
include/hw/virtio/virtio-pci.h | 4 ----
hw/virtio/virtio-pci.c | 6 +-----
2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h
index 1dbc3851b01..eb22ed0a1d9 100644
--- a/include/hw/virtio/virtio-pci.h
+++ b/include/hw/virtio/virtio-pci.h
@@ -32,7 +32,6 @@ DECLARE_OBJ_CHECKERS(VirtioPCIBusState, VirtioPCIBusClass,
enum {
VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT,
VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT,
- VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT,
VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT,
VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT,
VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT,
@@ -57,9 +56,6 @@ enum {
/* virtio version flags */
#define VIRTIO_PCI_FLAG_DISABLE_PCIE (1 << VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT)
-/* migrate extra state */
-#define VIRTIO_PCI_FLAG_MIGRATE_EXTRA (1 << VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT)
-
/* have pio notification for modern device ? */
#define VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY \
(1 << VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 9b48aa8c3e7..f52fac663c2 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -146,9 +146,7 @@ static const VMStateDescription vmstate_virtio_pci = {
static bool virtio_pci_has_extra_state(DeviceState *d)
{
- VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
-
- return proxy->flags & VIRTIO_PCI_FLAG_MIGRATE_EXTRA;
+ return true;
}
static void virtio_pci_save_extra_state(DeviceState *d, QEMUFile *f)
@@ -2363,8 +2361,6 @@ static void virtio_pci_bus_reset_hold(Object *obj, ResetType type)
static const Property virtio_pci_properties[] = {
DEFINE_PROP_BIT("virtio-pci-bus-master-bug-migration", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false),
- DEFINE_PROP_BIT("migrate-extra", VirtIOPCIProxy, flags,
- VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT, true),
DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false),
DEFINE_PROP_BIT("x-disable-pcie", VirtIOPCIProxy, flags,
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 16/27] hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (14 preceding siblings ...)
2025-05-28 10:04 ` [PULL 15/27] hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 17/27] hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines Thomas Huth
` (11 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
VIRTIO_PCI_FLAG_DISABLE_PCIE was only used by the hw_compat_2_4[]
array, via the 'x-disable-pcie=false' property. We removed all
machines using that array, lets remove all the code around
VIRTIO_PCI_FLAG_DISABLE_PCIE (see commit 9a4c0e220d8 for similar
VIRTIO_PCI_FLAG_* enum removal).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-9-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
include/hw/virtio/virtio-pci.h | 4 ----
hw/virtio/virtio-pci.c | 5 +----
2 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h
index eb22ed0a1d9..eab5394898d 100644
--- a/include/hw/virtio/virtio-pci.h
+++ b/include/hw/virtio/virtio-pci.h
@@ -33,7 +33,6 @@ enum {
VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT,
VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT,
VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT,
- VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT,
VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT,
VIRTIO_PCI_FLAG_ATS_BIT,
VIRTIO_PCI_FLAG_INIT_DEVERR_BIT,
@@ -53,9 +52,6 @@ enum {
* vcpu thread using ioeventfd for some devices. */
#define VIRTIO_PCI_FLAG_USE_IOEVENTFD (1 << VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT)
-/* virtio version flags */
-#define VIRTIO_PCI_FLAG_DISABLE_PCIE (1 << VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT)
-
/* have pio notification for modern device ? */
#define VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY \
(1 << VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index f52fac663c2..e62ae1e5e07 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -2363,8 +2363,6 @@ static const Property virtio_pci_properties[] = {
VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false),
DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false),
- DEFINE_PROP_BIT("x-disable-pcie", VirtIOPCIProxy, flags,
- VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, false),
DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false),
DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy,
@@ -2393,8 +2391,7 @@ static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp)
VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
PCIDevice *pci_dev = &proxy->pci_dev;
- if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE) &&
- virtio_pci_modern(proxy)) {
+ if (virtio_pci_modern(proxy)) {
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
}
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 17/27] hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (15 preceding siblings ...)
2025-05-28 10:04 ` [PULL 16/27] hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 18/27] hw/i386/x86: Remove X86MachineClass::save_tsc_khz field Thomas Huth
` (10 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Remove the now unused empty pc_compat_2_5[] array.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-10-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
include/hw/i386/pc.h | 3 ---
hw/i386/pc.c | 3 ---
hw/i386/pc_piix.c | 13 -------------
hw/i386/pc_q35.c | 13 -------------
4 files changed, 32 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index b34aa25fdce..79b72c54dd3 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -298,9 +298,6 @@ extern const size_t pc_compat_2_7_len;
extern GlobalProperty pc_compat_2_6[];
extern const size_t pc_compat_2_6_len;
-extern GlobalProperty pc_compat_2_5[];
-extern const size_t pc_compat_2_5_len;
-
#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
static void pc_machine_##suffix##_class_init(ObjectClass *oc, \
const void *data) \
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2b46714a5ac..cb375aabdc5 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -259,9 +259,6 @@ GlobalProperty pc_compat_2_6[] = {
};
const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
-GlobalProperty pc_compat_2_5[] = {};
-const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
-
/*
* @PC_FW_DATA:
* Size of the chunk of memory at the top of RAM for the BIOS ACPI tables
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 04213b45b44..7a62bb06500 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -778,19 +778,6 @@ static void pc_i440fx_machine_2_6_options(MachineClass *m)
DEFINE_I440FX_MACHINE(2, 6);
-static void pc_i440fx_machine_2_5_options(MachineClass *m)
-{
- X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
-
- pc_i440fx_machine_2_6_options(m);
- x86mc->save_tsc_khz = false;
- m->legacy_fw_cfg_order = 1;
- compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
- compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
-}
-
-DEFINE_I440FX_MACHINE(2, 5);
-
#ifdef CONFIG_ISAPC
static void isapc_machine_options(MachineClass *m)
{
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 47e12602413..33211b1876f 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -672,16 +672,3 @@ static void pc_q35_machine_2_6_options(MachineClass *m)
}
DEFINE_Q35_MACHINE(2, 6);
-
-static void pc_q35_machine_2_5_options(MachineClass *m)
-{
- X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
-
- pc_q35_machine_2_6_options(m);
- x86mc->save_tsc_khz = false;
- m->legacy_fw_cfg_order = 1;
- compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
- compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
-}
-
-DEFINE_Q35_MACHINE(2, 5);
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 18/27] hw/i386/x86: Remove X86MachineClass::save_tsc_khz field
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (16 preceding siblings ...)
2025-05-28 10:04 ` [PULL 17/27] hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:04 ` [PULL 19/27] hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE Thomas Huth
` (9 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The X86MachineClass::save_tsc_khz boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it and simplify tsc_khz_needed().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-11-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
include/hw/i386/x86.h | 5 -----
hw/i386/x86.c | 1 -
target/i386/machine.c | 5 ++---
3 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 258b1343a16..fc460b82f82 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -27,13 +27,8 @@
#include "qom/object.h"
struct X86MachineClass {
- /*< private >*/
MachineClass parent;
- /*< public >*/
-
- /* TSC rate migration: */
- bool save_tsc_khz;
/* use DMA capable linuxboot option rom */
bool fwcfg_dma_enabled;
/* CPU and apic information: */
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index e2d04092992..f80533df1c5 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -382,7 +382,6 @@ static void x86_machine_class_init(ObjectClass *oc, const void *data)
mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
mc->kvm_type = x86_kvm_type;
- x86mc->save_tsc_khz = true;
x86mc->fwcfg_dma_enabled = true;
nc->nmi_monitor_handler = x86_nmi;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 6cb561c6322..dd2dac1d443 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -1060,9 +1060,8 @@ static bool tsc_khz_needed(void *opaque)
{
X86CPU *cpu = opaque;
CPUX86State *env = &cpu->env;
- MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
- X86MachineClass *x86mc = X86_MACHINE_CLASS(mc);
- return env->tsc_khz && x86mc->save_tsc_khz;
+
+ return env->tsc_khz;
}
static const VMStateDescription vmstate_tsc_khz = {
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 19/27] hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (17 preceding siblings ...)
2025-05-28 10:04 ` [PULL 18/27] hw/i386/x86: Remove X86MachineClass::save_tsc_khz field Thomas Huth
@ 2025-05-28 10:04 ` Thomas Huth
2025-05-28 10:05 ` [PULL 20/27] hw/core/machine: Remove hw_compat_2_5[] array Thomas Huth
` (8 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:04 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The MachineClass::legacy_fw_cfg_order boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it along with:
- FW_CFG_ORDER_OVERRIDE_* definitions
- fw_cfg_set_order_override()
- fw_cfg_reset_order_override()
- fw_cfg_order[]
- rom_set_order_override()
- rom_reset_order_override()
Simplify CLI and pc_vga_init() / pc_nic_init().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-12-philmd@linaro.org>
[thuth: Fix error from check_patch.pl wrt to an empty "for" loop]
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
include/hw/boards.h | 3 +-
include/hw/loader.h | 2 -
include/hw/nvram/fw_cfg.h | 10 ----
hw/core/loader.c | 14 -----
hw/i386/pc.c | 7 +--
hw/nvram/fw_cfg.c | 110 +++-----------------------------------
system/vl.c | 5 --
7 files changed, 10 insertions(+), 141 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 03e7cbeae82..ab900dacabc 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -286,8 +286,7 @@ struct MachineClass {
no_parallel:1,
no_floppy:1,
no_cdrom:1,
- pci_allow_0_address:1,
- legacy_fw_cfg_order:1;
+ pci_allow_0_address:1;
bool auto_create_sdcard;
bool is_default;
const char *default_machine_opts;
diff --git a/include/hw/loader.h b/include/hw/loader.h
index d280dc33e96..c96b5e141c6 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -270,8 +270,6 @@ int rom_add_elf_program(const char *name, GMappedFile *mapped_file, void *data,
AddressSpace *as);
int rom_check_and_register_reset(void);
void rom_set_fw(FWCfgState *f);
-void rom_set_order_override(int order);
-void rom_reset_order_override(void);
/**
* rom_transaction_begin:
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index 47578ccc7f2..d41b9328fd1 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -42,14 +42,6 @@ struct FWCfgDataGeneratorClass {
typedef struct fw_cfg_file FWCfgFile;
-#define FW_CFG_ORDER_OVERRIDE_VGA 70
-#define FW_CFG_ORDER_OVERRIDE_NIC 80
-#define FW_CFG_ORDER_OVERRIDE_USER 100
-#define FW_CFG_ORDER_OVERRIDE_DEVICE 110
-
-void fw_cfg_set_order_override(FWCfgState *fw_cfg, int order);
-void fw_cfg_reset_order_override(FWCfgState *fw_cfg);
-
typedef struct FWCfgFiles {
uint32_t count;
FWCfgFile f[];
@@ -75,8 +67,6 @@ struct FWCfgState {
uint32_t cur_offset;
Notifier machine_ready;
- int fw_cfg_order_override;
-
bool dma_enabled;
dma_addr_t dma_addr;
AddressSpace *dma_as;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index b792a54bb02..e7056ba4bd3 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -1333,20 +1333,6 @@ void rom_set_fw(FWCfgState *f)
fw_cfg = f;
}
-void rom_set_order_override(int order)
-{
- if (!fw_cfg)
- return;
- fw_cfg_set_order_override(fw_cfg, order);
-}
-
-void rom_reset_order_override(void)
-{
- if (!fw_cfg)
- return;
- fw_cfg_reset_order_override(fw_cfg);
-}
-
void rom_transaction_begin(void)
{
Rom *rom;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index cb375aabdc5..49632b69d29 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1033,7 +1033,6 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
{
DeviceState *dev = NULL;
- rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
if (pci_bus) {
PCIDevice *pcidev = pci_vga_init(pci_bus);
dev = pcidev ? &pcidev->qdev : NULL;
@@ -1041,7 +1040,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
ISADevice *isadev = isa_vga_init(isa_bus);
dev = isadev ? DEVICE(isadev) : NULL;
}
- rom_reset_order_override();
+
return dev;
}
@@ -1231,8 +1230,6 @@ void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000);
NICInfo *nd;
- rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
-
while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) {
pc_init_ne2k_isa(isa_bus, nd, &error_fatal);
}
@@ -1241,8 +1238,6 @@ void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
if (pci_bus) {
pci_init_nic_devices(pci_bus, mc->default_nic);
}
-
- rom_reset_order_override();
}
void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 237b9f7d1fe..aa240504935 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -817,62 +817,6 @@ void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value)
g_free(old);
}
-void fw_cfg_set_order_override(FWCfgState *s, int order)
-{
- assert(s->fw_cfg_order_override == 0);
- s->fw_cfg_order_override = order;
-}
-
-void fw_cfg_reset_order_override(FWCfgState *s)
-{
- assert(s->fw_cfg_order_override != 0);
- s->fw_cfg_order_override = 0;
-}
-
-/*
- * This is the legacy order list. For legacy systems, files are in
- * the fw_cfg in the order defined below, by the "order" value. Note
- * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a
- * specific area, but there may be more than one and they occur in the
- * order that the user specifies them on the command line. Those are
- * handled in a special manner, using the order override above.
- *
- * For non-legacy, the files are sorted by filename to avoid this kind
- * of complexity in the future.
- *
- * This is only for x86, other arches don't implement versioning so
- * they won't set legacy mode.
- */
-static struct {
- const char *name;
- int order;
-} fw_cfg_order[] = {
- { "etc/boot-menu-wait", 10 },
- { "bootsplash.jpg", 11 },
- { "bootsplash.bmp", 12 },
- { "etc/boot-fail-wait", 15 },
- { "etc/smbios/smbios-tables", 20 },
- { "etc/smbios/smbios-anchor", 30 },
- { "etc/e820", 40 },
- { "etc/reserved-memory-end", 50 },
- { "genroms/kvmvapic.bin", 55 },
- { "genroms/linuxboot.bin", 60 },
- { }, /* VGA ROMs from pc_vga_init come here, 70. */
- { }, /* NIC option ROMs from pc_nic_init come here, 80. */
- { "etc/system-states", 90 },
- { }, /* User ROMs come here, 100. */
- { }, /* Device FW comes here, 110. */
- { "etc/extra-pci-roots", 120 },
- { "etc/acpi/tables", 130 },
- { "etc/table-loader", 140 },
- { "etc/tpm/log", 150 },
- { "etc/acpi/rsdp", 160 },
- { "bootorder", 170 },
- { "etc/msr_feature_control", 180 },
-
-#define FW_CFG_ORDER_OVERRIDE_LAST 200
-};
-
/*
* Any sub-page size update to these table MRs will be lost during migration,
* as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path.
@@ -890,29 +834,6 @@ static void fw_cfg_acpi_mr_save(FWCfgState *s, const char *filename, size_t len)
}
}
-static int get_fw_cfg_order(FWCfgState *s, const char *name)
-{
- int i;
-
- if (s->fw_cfg_order_override > 0) {
- return s->fw_cfg_order_override;
- }
-
- for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) {
- if (fw_cfg_order[i].name == NULL) {
- continue;
- }
-
- if (strcmp(name, fw_cfg_order[i].name) == 0) {
- return fw_cfg_order[i].order;
- }
- }
-
- /* Stick unknown stuff at the end. */
- warn_report("Unknown firmware file in legacy mode: %s", name);
- return FW_CFG_ORDER_OVERRIDE_LAST;
-}
-
void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
FWCfgCallback select_cb,
FWCfgWriteCallback write_cb,
@@ -921,7 +842,6 @@ void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
{
int i, index, count;
size_t dsize;
- MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
int order = 0;
if (!s->files) {
@@ -933,22 +853,11 @@ void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
count = be32_to_cpu(s->files->count);
assert(count < fw_cfg_file_slots(s));
- /* Find the insertion point. */
- if (mc->legacy_fw_cfg_order) {
- /*
- * Sort by order. For files with the same order, we keep them
- * in the sequence in which they were added.
- */
- order = get_fw_cfg_order(s, filename);
- for (index = count;
- index > 0 && order < s->entry_order[index - 1];
- index--);
- } else {
- /* Sort by file name. */
- for (index = count;
- index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
- index--);
- }
+ /* Find the insertion point, sorting by file name. */
+ for (index = count;
+ index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
+ index--)
+ ;
/*
* Move all the entries from the index point and after down one
@@ -1058,7 +967,6 @@ bool fw_cfg_add_file_from_generator(FWCfgState *s,
static void fw_cfg_machine_reset(void *opaque)
{
- MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
FWCfgState *s = opaque;
void *ptr;
size_t len;
@@ -1068,11 +976,9 @@ static void fw_cfg_machine_reset(void *opaque)
ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)buf, len);
g_free(ptr);
- if (!mc->legacy_fw_cfg_order) {
- buf = get_boot_devices_lchs_list(&len);
- ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len);
- g_free(ptr);
- }
+ buf = get_boot_devices_lchs_list(&len);
+ ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len);
+ g_free(ptr);
}
static void fw_cfg_machine_ready(struct Notifier *n, void *data)
diff --git a/system/vl.c b/system/vl.c
index fd402b8ff8f..3b7057e6c66 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -1192,10 +1192,7 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, Error **errp)
return -1;
}
}
- /* For legacy, keep user files in a specific global order. */
- fw_cfg_set_order_override(fw_cfg, FW_CFG_ORDER_OVERRIDE_USER);
fw_cfg_add_file(fw_cfg, name, buf, size);
- fw_cfg_reset_order_override(fw_cfg);
return 0;
}
@@ -2745,7 +2742,6 @@ static void qemu_create_cli_devices(void)
}
/* init generic devices */
- rom_set_order_override(FW_CFG_ORDER_OVERRIDE_DEVICE);
qemu_opts_foreach(qemu_find_opts("device"),
device_init_func, NULL, &error_fatal);
QTAILQ_FOREACH(opt, &device_opts, next) {
@@ -2756,7 +2752,6 @@ static void qemu_create_cli_devices(void)
assert(ret_data == NULL); /* error_fatal aborts */
loc_pop(&opt->loc);
}
- rom_reset_order_override();
}
static bool qemu_machine_creation_done(Error **errp)
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 20/27] hw/core/machine: Remove hw_compat_2_5[] array
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (18 preceding siblings ...)
2025-05-28 10:04 ` [PULL 19/27] hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE Thomas Huth
@ 2025-05-28 10:05 ` Thomas Huth
2025-05-28 10:05 ` [PULL 21/27] hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition Thomas Huth
` (7 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:05 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The hw_compat_2_5[] array was only used by the pc-q35-2.5 and
pc-i440fx-2.5 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-13-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
include/hw/boards.h | 3 ---
hw/core/machine.c | 9 ---------
2 files changed, 12 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index ab900dacabc..f424b2b5058 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -862,7 +862,4 @@ extern const size_t hw_compat_2_7_len;
extern GlobalProperty hw_compat_2_6[];
extern const size_t hw_compat_2_6_len;
-extern GlobalProperty hw_compat_2_5[];
-extern const size_t hw_compat_2_5_len;
-
#endif
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 15cd2bc3c40..e869821b224 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -285,15 +285,6 @@ GlobalProperty hw_compat_2_6[] = {
};
const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
-GlobalProperty hw_compat_2_5[] = {
- { "isa-fdc", "fallback", "144" },
- { "pvscsi", "x-old-pci-configuration", "on" },
- { "pvscsi", "x-disable-pcie", "on" },
- { "vmxnet3", "x-old-msi-offsets", "on" },
- { "vmxnet3", "x-disable-pcie", "on" },
-};
-const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
-
MachineState *current_machine;
static char *machine_get_kernel(Object *obj, Error **errp)
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 21/27] hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (19 preceding siblings ...)
2025-05-28 10:05 ` [PULL 20/27] hw/core/machine: Remove hw_compat_2_5[] array Thomas Huth
@ 2025-05-28 10:05 ` Thomas Huth
2025-05-28 10:05 ` [PULL 22/27] hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition Thomas Huth
` (6 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:05 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
PVSCSI_COMPAT_OLD_PCI_CONFIGURATION was only used by the
hw_compat_2_5[] array, via the 'x-old-pci-configuration=on'
property. We removed all machines using that array, lets remove
all the code around PVSCSI_COMPAT_OLD_PCI_CONFIGURATION.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-15-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
hw/scsi/vmw_pvscsi.c | 26 +++++++-------------------
1 file changed, 7 insertions(+), 19 deletions(-)
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index d5825b67868..34de59a7cf6 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -69,17 +69,11 @@ OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI)
/* Compatibility flags for migration */
-#define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
-#define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
- (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
#define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
#define PVSCSI_COMPAT_DISABLE_PCIE \
(1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
-#define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
- ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
-#define PVSCSI_MSI_OFFSET(s) \
- (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
+#define PVSCSI_MSI_OFFSET (0x7c)
#define PVSCSI_EXP_EP_OFFSET (0x40)
typedef struct PVSCSIRingInfo {
@@ -1110,7 +1104,7 @@ pvscsi_init_msi(PVSCSIState *s)
int res;
PCIDevice *d = PCI_DEVICE(s);
- res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS,
+ res = msi_init(d, PVSCSI_MSI_OFFSET, PVSCSI_MSIX_NUM_VECTORS,
PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL);
if (res < 0) {
trace_pvscsi_init_msi_fail(res);
@@ -1158,15 +1152,11 @@ pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
trace_pvscsi_state("init");
/* PCI subsystem ID, subsystem vendor ID, revision */
- if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) {
- pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000);
- } else {
- pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
- PCI_VENDOR_ID_VMWARE);
- pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
- PCI_DEVICE_ID_VMWARE_PVSCSI);
- pci_config_set_revision(pci_dev->config, 0x2);
- }
+ pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
+ PCI_VENDOR_ID_VMWARE);
+ pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
+ PCI_DEVICE_ID_VMWARE_PVSCSI);
+ pci_config_set_revision(pci_dev->config, 0x2);
/* PCI latency timer = 255 */
pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
@@ -1298,8 +1288,6 @@ static const VMStateDescription vmstate_pvscsi = {
static const Property pvscsi_properties[] = {
DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
- DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
- PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
};
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 22/27] hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (20 preceding siblings ...)
2025-05-28 10:05 ` [PULL 21/27] hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition Thomas Huth
@ 2025-05-28 10:05 ` Thomas Huth
2025-05-28 10:05 ` [PULL 23/27] hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit Thomas Huth
` (5 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:05 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
PVSCSI_COMPAT_DISABLE_PCIE_BIT was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around PVSCSI_COMPAT_DISABLE_PCIE_BIT, including the now
unused PVSCSIState::compat_flags field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-16-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
hw/scsi/vmw_pvscsi.c | 30 +-----------------------------
1 file changed, 1 insertion(+), 29 deletions(-)
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 34de59a7cf6..e163023d14c 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -68,11 +68,6 @@ struct PVSCSIClass {
OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI)
-/* Compatibility flags for migration */
-#define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
-#define PVSCSI_COMPAT_DISABLE_PCIE \
- (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
-
#define PVSCSI_MSI_OFFSET (0x7c)
#define PVSCSI_EXP_EP_OFFSET (0x40)
@@ -123,8 +118,6 @@ struct PVSCSIState {
uint8_t msi_used; /* For migration compatibility */
PVSCSIRingInfo rings; /* Data transfer rings manager */
uint32_t resetting; /* Reset in progress */
-
- uint32_t compat_flags;
};
typedef struct PVSCSIRequest {
@@ -1224,21 +1217,8 @@ pvscsi_post_load(void *opaque, int version_id)
return 0;
}
-static bool pvscsi_vmstate_need_pcie_device(void *opaque)
-{
- PVSCSIState *s = PVSCSI(opaque);
-
- return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
-}
-
-static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
-{
- return !pvscsi_vmstate_need_pcie_device(opaque);
-}
-
static const VMStateDescription vmstate_pvscsi_pcie_device = {
.name = "pvscsi/pcie",
- .needed = pvscsi_vmstate_need_pcie_device,
.fields = (const VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState),
VMSTATE_END_OF_LIST()
@@ -1252,9 +1232,6 @@ static const VMStateDescription vmstate_pvscsi = {
.pre_save = pvscsi_pre_save,
.post_load = pvscsi_post_load,
.fields = (const VMStateField[]) {
- VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
- pvscsi_vmstate_test_pci_device, 0,
- vmstate_pci_device, PCIDevice),
VMSTATE_UINT8(msi_used, PVSCSIState),
VMSTATE_UINT32(resetting, PVSCSIState),
VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
@@ -1288,19 +1265,14 @@ static const VMStateDescription vmstate_pvscsi = {
static const Property pvscsi_properties[] = {
DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
- DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
- PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
};
static void pvscsi_realize(DeviceState *qdev, Error **errp)
{
PVSCSIClass *pvs_c = PVSCSI_GET_CLASS(qdev);
PCIDevice *pci_dev = PCI_DEVICE(qdev);
- PVSCSIState *s = PVSCSI(qdev);
- if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
- pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
- }
+ pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
pvs_c->parent_dc_realize(qdev, errp);
}
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 23/27] hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (21 preceding siblings ...)
2025-05-28 10:05 ` [PULL 22/27] hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition Thomas Huth
@ 2025-05-28 10:05 ` Thomas Huth
2025-05-28 10:05 ` [PULL 24/27] hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition Thomas Huth
` (4 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:05 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Simplify replacing pvscsi_realize() by pvscsi_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-17-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
hw/scsi/vmw_pvscsi.c | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index e163023d14c..7c98b1b8ea6 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -1267,21 +1267,15 @@ static const Property pvscsi_properties[] = {
DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
};
-static void pvscsi_realize(DeviceState *qdev, Error **errp)
+static void pvscsi_instance_init(Object *obj)
{
- PVSCSIClass *pvs_c = PVSCSI_GET_CLASS(qdev);
- PCIDevice *pci_dev = PCI_DEVICE(qdev);
-
- pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
-
- pvs_c->parent_dc_realize(qdev, errp);
+ PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
}
static void pvscsi_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- PVSCSIClass *pvs_k = PVSCSI_CLASS(klass);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
k->realize = pvscsi_realizefn;
@@ -1290,8 +1284,6 @@ static void pvscsi_class_init(ObjectClass *klass, const void *data)
k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
k->class_id = PCI_CLASS_STORAGE_SCSI;
k->subsystem_id = 0x1000;
- device_class_set_parent_realize(dc, pvscsi_realize,
- &pvs_k->parent_dc_realize);
device_class_set_legacy_reset(dc, pvscsi_reset);
dc->vmsd = &vmstate_pvscsi;
device_class_set_props(dc, pvscsi_properties);
@@ -1306,6 +1298,7 @@ static const TypeInfo pvscsi_info = {
.class_size = sizeof(PVSCSIClass),
.instance_size = sizeof(PVSCSIState),
.class_init = pvscsi_class_init,
+ .instance_init = pvscsi_instance_init,
.interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
{ INTERFACE_PCIE_DEVICE },
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 24/27] hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (22 preceding siblings ...)
2025-05-28 10:05 ` [PULL 23/27] hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit Thomas Huth
@ 2025-05-28 10:05 ` Thomas Huth
2025-05-28 10:05 ` [PULL 25/27] hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition Thomas Huth
` (3 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:05 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS was only used by the
hw_compat_2_5[] array, via the 'x-old-msi-offsets=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-18-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
hw/net/vmxnet3.c | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 83d942af179..3cf5d71f478 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -42,18 +42,13 @@
#define VMXNET3_MSIX_BAR_SIZE 0x2000
/* Compatibility flags for migration */
-#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
-#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
- (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
(1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
#define VMXNET3_EXP_EP_OFFSET (0x48)
-#define VMXNET3_MSI_OFFSET(s) \
- ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
-#define VMXNET3_MSIX_OFFSET(s) \
- ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
+#define VMXNET3_MSI_OFFSET (0x84)
+#define VMXNET3_MSIX_OFFSET (0x9c)
#define VMXNET3_DSN_OFFSET (0x100)
#define VMXNET3_BAR0_IDX (0)
@@ -61,8 +56,7 @@
#define VMXNET3_MSIX_BAR_IDX (2)
#define VMXNET3_OFF_MSIX_TABLE (0x000)
-#define VMXNET3_OFF_MSIX_PBA(s) \
- ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
+#define VMXNET3_OFF_MSIX_PBA (0x1000)
/* Link speed in Mbps should be shifted by 16 */
#define VMXNET3_LINK_SPEED (1000 << 16)
@@ -2122,8 +2116,8 @@ vmxnet3_init_msix(VMXNET3State *s)
&s->msix_bar,
VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
&s->msix_bar,
- VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s),
- VMXNET3_MSIX_OFFSET(s), NULL);
+ VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
+ VMXNET3_MSIX_OFFSET, NULL);
if (0 > res) {
VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
@@ -2221,7 +2215,7 @@ static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
/* Interrupt pin A */
pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
- ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS,
+ ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET, VMXNET3_MAX_NMSIX_INTRS,
VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL);
/* Any error other than -ENOTSUP(board's MSI support is broken)
* is a programming error. Fall back to INTx silently on -ENOTSUP */
@@ -2472,8 +2466,6 @@ static const VMStateDescription vmstate_vmxnet3 = {
static const Property vmxnet3_properties[] = {
DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
- DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags,
- VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false),
DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags,
VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false),
};
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 25/27] hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (23 preceding siblings ...)
2025-05-28 10:05 ` [PULL 24/27] hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition Thomas Huth
@ 2025-05-28 10:05 ` Thomas Huth
2025-05-28 10:05 ` [PULL 26/27] hw/net/vmxnet3: Merge DeviceRealize in InstanceInit Thomas Huth
` (2 subsequent siblings)
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:05 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
VMXNET3_COMPAT_FLAG_DISABLE_PCIE was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_DISABLE_PCIE.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-19-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
hw/net/vmxnet3.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 3cf5d71f478..d080fe9b38a 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -41,11 +41,6 @@
#define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
#define VMXNET3_MSIX_BAR_SIZE 0x2000
-/* Compatibility flags for migration */
-#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
-#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
- (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
-
#define VMXNET3_EXP_EP_OFFSET (0x48)
#define VMXNET3_MSI_OFFSET (0x84)
#define VMXNET3_MSIX_OFFSET (0x9c)
@@ -2466,8 +2461,6 @@ static const VMStateDescription vmstate_vmxnet3 = {
static const Property vmxnet3_properties[] = {
DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
- DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags,
- VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false),
};
static void vmxnet3_realize(DeviceState *qdev, Error **errp)
@@ -2476,9 +2469,7 @@ static void vmxnet3_realize(DeviceState *qdev, Error **errp)
PCIDevice *pci_dev = PCI_DEVICE(qdev);
VMXNET3State *s = VMXNET3(qdev);
- if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) {
- pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
- }
+ pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
vc->parent_dc_realize(qdev, errp);
}
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 26/27] hw/net/vmxnet3: Merge DeviceRealize in InstanceInit
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (24 preceding siblings ...)
2025-05-28 10:05 ` [PULL 25/27] hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition Thomas Huth
@ 2025-05-28 10:05 ` Thomas Huth
2025-05-28 10:05 ` [PULL 27/27] tests/unit/test-util-sockets: fix mem-leak on error object Thomas Huth
2025-05-28 19:23 ` [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Stefan Hajnoczi
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:05 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Hajnoczi, Philippe Mathieu-Daudé,
Daniel P. Berrangé, Zhao Liu, Xiaoyao Li
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Simplify merging vmxnet3_realize() within vmxnet3_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20250512083948.39294-20-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
hw/net/vmxnet3.c | 15 +--------------
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index d080fe9b38a..7c0ca56b7c0 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -2238,6 +2238,7 @@ static void vmxnet3_instance_init(Object *obj)
device_add_bootindex_property(obj, &s->conf.bootindex,
"bootindex", "/ethernet-phy@0",
DEVICE(obj));
+ PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
}
static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
@@ -2463,22 +2464,10 @@ static const Property vmxnet3_properties[] = {
DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
};
-static void vmxnet3_realize(DeviceState *qdev, Error **errp)
-{
- VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev);
- PCIDevice *pci_dev = PCI_DEVICE(qdev);
- VMXNET3State *s = VMXNET3(qdev);
-
- pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
-
- vc->parent_dc_realize(qdev, errp);
-}
-
static void vmxnet3_class_init(ObjectClass *class, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(class);
PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
- VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class);
c->realize = vmxnet3_pci_realize;
c->exit = vmxnet3_pci_uninit;
@@ -2489,8 +2478,6 @@ static void vmxnet3_class_init(ObjectClass *class, const void *data)
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
- device_class_set_parent_realize(dc, vmxnet3_realize,
- &vc->parent_dc_realize);
dc->desc = "VMWare Paravirtualized Ethernet v3";
device_class_set_legacy_reset(dc, vmxnet3_qdev_reset);
dc->vmsd = &vmstate_vmxnet3;
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 27/27] tests/unit/test-util-sockets: fix mem-leak on error object
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (25 preceding siblings ...)
2025-05-28 10:05 ` [PULL 26/27] hw/net/vmxnet3: Merge DeviceRealize in InstanceInit Thomas Huth
@ 2025-05-28 10:05 ` Thomas Huth
2025-05-28 19:23 ` [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Stefan Hajnoczi
27 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 10:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Stefan Hajnoczi, Matheus Tavares Bernardino, Juraj Marcin
From: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
The test fails with --enable-asan as the error struct is never freed.
In the case where the test expects a success but it fails, let's also
report the error for debugging (it will be freed internally).
Fixes 316e8ee8d6 ("util/qemu-sockets: Refactor inet_parse() to use QemuOpts")
Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Reviewed-by: Juraj Marcin <jmarcin@redhat.com>
Message-ID: <518d94c7db20060b2a086cf55ee9bffab992a907.1748280011.git.matheus.bernardino@oss.qualcomm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
tests/unit/test-util-sockets.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/tests/unit/test-util-sockets.c b/tests/unit/test-util-sockets.c
index 8492f4d68f2..ee66d727c38 100644
--- a/tests/unit/test-util-sockets.c
+++ b/tests/unit/test-util-sockets.c
@@ -341,8 +341,12 @@ static void inet_parse_test_helper(const char *str,
int rc = inet_parse(&addr, str, &error);
if (success) {
+ if (error) {
+ error_report_err(error);
+ }
g_assert_cmpint(rc, ==, 0);
} else {
+ error_free(error);
g_assert_cmpint(rc, <, 0);
}
if (exp_addr != NULL) {
--
2.49.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups
2025-05-28 10:04 [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Thomas Huth
` (26 preceding siblings ...)
2025-05-28 10:05 ` [PULL 27/27] tests/unit/test-util-sockets: fix mem-leak on error object Thomas Huth
@ 2025-05-28 19:23 ` Stefan Hajnoczi
2025-05-28 20:12 ` Thomas Huth
27 siblings, 1 reply; 33+ messages in thread
From: Stefan Hajnoczi @ 2025-05-28 19:23 UTC (permalink / raw)
To: Thomas Huth; +Cc: qemu-devel, Stefan Hajnoczi
On Wed, May 28, 2025 at 6:12 AM Thomas Huth <thuth@redhat.com> wrote:
>
> Hi!
>
> The following changes since commit 80db93b2b88f9b3ed8927ae7ac74ca30e643a83e:
>
> Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into staging (2025-05-26 10:16:59 -0400)
>
> are available in the Git repository at:
>
> https://gitlab.com/thuth/qemu.git tags/pull-request-2025-05-28
>
> for you to fetch changes up to 9c2da02e184fddfa7cd7d7813455c2306daae99a:
>
> tests/unit/test-util-sockets: fix mem-leak on error object (2025-05-28 11:59:47 +0200)
>
> ----------------------------------------------------------------
> * Functional tests improvements
> * Endianness improvements/clean-ups for the Microblaze machines
> * Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and related code
>
> ----------------------------------------------------------------
> Alexandr Moshkov (2):
> tests/functional: add skipLockedMemoryTest decorator
> tests/functional: add memlock tests
Hi Thomas and Alexandr,
The memlock tests are failing:
https://gitlab.com/qemu-project/qemu/-/jobs/10181084830#L5421
https://gitlab.com/qemu-project/qemu/-/jobs/10181084865#L5476
Please take a look and send a new pull request. Thanks!
Stefan
>
> Matheus Tavares Bernardino (1):
> tests/unit/test-util-sockets: fix mem-leak on error object
>
> Philippe Mathieu-Daudé (17):
> hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines
> hw/i386/pc: Remove PCMachineClass::broken_reserved_end field
> hw/i386/pc: Remove pc_compat_2_4[] array
> hw/core/machine: Remove hw_compat_2_4[] array
> hw/net/e1000: Remove unused E1000_FLAG_MAC flag
> hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition
> hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition
> hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines
> hw/i386/x86: Remove X86MachineClass::save_tsc_khz field
> hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE
> hw/core/machine: Remove hw_compat_2_5[] array
> hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition
> hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition
> hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit
> hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition
> hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition
> hw/net/vmxnet3: Merge DeviceRealize in InstanceInit
>
> Thomas Huth (7):
> tests/functional/test_sparc64_tuxrun: Explicitly set the 'sun4u' machine
> tests/functional/test_mips_malta: Re-enable the check for the PCI host bridge
> tests/functional/test_mem_addr_space: Use set_machine() to select the machine
> hw/microblaze: Add endianness property to the petalogix_s3adsp1800 machine
> tests/functional: Test both microblaze s3adsp1800 endianness variants
> hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu
> docs: Deprecate the qemu-system-microblazeel binary
>
> docs/about/deprecated.rst | 19 ++--
> docs/about/removed-features.rst | 9 ++
> include/hw/boards.h | 9 +-
> include/hw/i386/pc.h | 7 --
> include/hw/i386/x86.h | 5 --
> include/hw/loader.h | 2 -
> include/hw/nvram/fw_cfg.h | 10 ---
> include/hw/virtio/virtio-pci.h | 8 --
> hw/core/loader.c | 14 ---
> hw/core/machine.c | 18 ----
> hw/i386/pc.c | 42 ++-------
> hw/i386/pc_piix.c | 26 ------
> hw/i386/pc_q35.c | 26 ------
> hw/i386/x86.c | 1 -
> hw/microblaze/petalogix_ml605_mmu.c | 15 +---
> hw/microblaze/petalogix_s3adsp1800_mmu.c | 41 +++++++--
> hw/microblaze/xlnx-zynqmp-pmu.c | 7 +-
> hw/net/e1000.c | 95 +++++++++-----------
> hw/net/vmxnet3.c | 44 ++-------
> hw/nvram/fw_cfg.c | 110 ++---------------------
> hw/scsi/vmw_pvscsi.c | 67 +++-----------
> hw/virtio/virtio-pci.c | 11 +--
> system/vl.c | 5 --
> target/i386/machine.c | 5 +-
> tests/qtest/test-x86-cpuid-compat.c | 14 ---
> tests/unit/test-util-sockets.c | 4 +
> tests/functional/meson.build | 1 +
> tests/functional/qemu_test/__init__.py | 2 +-
> tests/functional/qemu_test/decorators.py | 18 ++++
> tests/functional/test_mem_addr_space.py | 63 ++++++-------
> tests/functional/test_memlock.py | 79 ++++++++++++++++
> tests/functional/test_microblaze_s3adsp1800.py | 18 ++--
> tests/functional/test_microblazeel_s3adsp1800.py | 6 +-
> tests/functional/test_mips_malta.py | 6 +-
> tests/functional/test_sparc64_tuxrun.py | 1 +
> 35 files changed, 296 insertions(+), 512 deletions(-)
> create mode 100755 tests/functional/test_memlock.py
>
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups
2025-05-28 19:23 ` [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups Stefan Hajnoczi
@ 2025-05-28 20:12 ` Thomas Huth
2025-06-04 7:51 ` Alexandr Moshkov
0 siblings, 1 reply; 33+ messages in thread
From: Thomas Huth @ 2025-05-28 20:12 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-devel, Stefan Hajnoczi
On 28/05/2025 21.23, Stefan Hajnoczi wrote:
> On Wed, May 28, 2025 at 6:12 AM Thomas Huth <thuth@redhat.com> wrote:
>>
>> Hi!
>>
>> The following changes since commit 80db93b2b88f9b3ed8927ae7ac74ca30e643a83e:
>>
>> Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into staging (2025-05-26 10:16:59 -0400)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.com/thuth/qemu.git tags/pull-request-2025-05-28
>>
>> for you to fetch changes up to 9c2da02e184fddfa7cd7d7813455c2306daae99a:
>>
>> tests/unit/test-util-sockets: fix mem-leak on error object (2025-05-28 11:59:47 +0200)
>>
>> ----------------------------------------------------------------
>> * Functional tests improvements
>> * Endianness improvements/clean-ups for the Microblaze machines
>> * Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and related code
>>
>> ----------------------------------------------------------------
>> Alexandr Moshkov (2):
>> tests/functional: add skipLockedMemoryTest decorator
>> tests/functional: add memlock tests
>
> Hi Thomas and Alexandr,
> The memlock tests are failing:
> https://gitlab.com/qemu-project/qemu/-/jobs/10181084830#L5421
> https://gitlab.com/qemu-project/qemu/-/jobs/10181084865#L5476
>
> Please take a look and send a new pull request. Thanks!
According to the log:
Output: qemu-system-aarch64: No machine specified, and there is no default
I think it likely does not make sense to run this test with the aarch64
target... Alexandr, would it make sense to limit this to x86 only?
Also, quite a bunch of other tests failed at the same time in the aarch64
job, too ... I wonder whether they were running out of memory now?
Thomas
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups
2025-05-28 20:12 ` Thomas Huth
@ 2025-06-04 7:51 ` Alexandr Moshkov
2025-06-04 13:11 ` Stefan Hajnoczi
0 siblings, 1 reply; 33+ messages in thread
From: Alexandr Moshkov @ 2025-06-04 7:51 UTC (permalink / raw)
To: Thomas Huth, Stefan Hajnoczi
Cc: qemu-devel, Stefan Hajnoczi, Alexandr Moshkov
On 5/29/25 01:12, Thomas Huth wrote:
> On 28/05/2025 21.23, Stefan Hajnoczi wrote:
>> On Wed, May 28, 2025 at 6:12 AM Thomas Huth <thuth@redhat.com> wrote:
>>>
>>> Hi!
>>>
>>> The following changes since commit
>>> 80db93b2b88f9b3ed8927ae7ac74ca30e643a83e:
>>>
>>> Merge tag 'pull-aspeed-20250526' of
>>> https://github.com/legoater/qemu into staging (2025-05-26 10:16:59
>>> -0400)
>>>
>>> are available in the Git repository at:
>>>
>>> https://gitlab.com/thuth/qemu.git tags/pull-request-2025-05-28
>>>
>>> for you to fetch changes up to
>>> 9c2da02e184fddfa7cd7d7813455c2306daae99a:
>>>
>>> tests/unit/test-util-sockets: fix mem-leak on error object
>>> (2025-05-28 11:59:47 +0200)
>>>
>>> ----------------------------------------------------------------
>>> * Functional tests improvements
>>> * Endianness improvements/clean-ups for the Microblaze machines
>>> * Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and
>>> related code
>>>
>>> ----------------------------------------------------------------
>>> Alexandr Moshkov (2):
>>> tests/functional: add skipLockedMemoryTest decorator
>>> tests/functional: add memlock tests
>>
>> Hi Thomas and Alexandr,
>> The memlock tests are failing:
>> https://gitlab.com/qemu-project/qemu/-/jobs/10181084830#L5421
>> https://gitlab.com/qemu-project/qemu/-/jobs/10181084865#L5476
>>
>> Please take a look and send a new pull request. Thanks!
>
Hello! I think Stefan forgot to CC me in his reply. Only now find this
message)
> According to the log:
>
> Output: qemu-system-aarch64: No machine specified, and there is no
> default
>
> I think it likely does not make sense to run this test with the
> aarch64 target... Alexandr, would it make sense to limit this to x86
> only?
It looks like adding this lines to vm creation fixes all problems with
other targets on memlock test:
self.set_machine('none')
self.vm.add_args('-nodefaults')
What's the convenient way to fix it? Resend a new patch?
Best regards,
Alexandr
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups
2025-06-04 7:51 ` Alexandr Moshkov
@ 2025-06-04 13:11 ` Stefan Hajnoczi
2025-06-04 13:19 ` Thomas Huth
0 siblings, 1 reply; 33+ messages in thread
From: Stefan Hajnoczi @ 2025-06-04 13:11 UTC (permalink / raw)
To: Alexandr Moshkov; +Cc: Thomas Huth, qemu-devel, Stefan Hajnoczi
On Wed, Jun 4, 2025 at 3:51 AM Alexandr Moshkov
<dtalexundeer@yandex-team.ru> wrote:
>
>
> On 5/29/25 01:12, Thomas Huth wrote:
> > On 28/05/2025 21.23, Stefan Hajnoczi wrote:
> >> On Wed, May 28, 2025 at 6:12 AM Thomas Huth <thuth@redhat.com> wrote:
> >>>
> >>> Hi!
> >>>
> >>> The following changes since commit
> >>> 80db93b2b88f9b3ed8927ae7ac74ca30e643a83e:
> >>>
> >>> Merge tag 'pull-aspeed-20250526' of
> >>> https://github.com/legoater/qemu into staging (2025-05-26 10:16:59
> >>> -0400)
> >>>
> >>> are available in the Git repository at:
> >>>
> >>> https://gitlab.com/thuth/qemu.git tags/pull-request-2025-05-28
> >>>
> >>> for you to fetch changes up to
> >>> 9c2da02e184fddfa7cd7d7813455c2306daae99a:
> >>>
> >>> tests/unit/test-util-sockets: fix mem-leak on error object
> >>> (2025-05-28 11:59:47 +0200)
> >>>
> >>> ----------------------------------------------------------------
> >>> * Functional tests improvements
> >>> * Endianness improvements/clean-ups for the Microblaze machines
> >>> * Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and
> >>> related code
> >>>
> >>> ----------------------------------------------------------------
> >>> Alexandr Moshkov (2):
> >>> tests/functional: add skipLockedMemoryTest decorator
> >>> tests/functional: add memlock tests
> >>
> >> Hi Thomas and Alexandr,
> >> The memlock tests are failing:
> >> https://gitlab.com/qemu-project/qemu/-/jobs/10181084830#L5421
> >> https://gitlab.com/qemu-project/qemu/-/jobs/10181084865#L5476
> >>
> >> Please take a look and send a new pull request. Thanks!
> >
> Hello! I think Stefan forgot to CC me in his reply. Only now find this
> message)
>
>
> > According to the log:
> >
> > Output: qemu-system-aarch64: No machine specified, and there is no
> > default
> >
> > I think it likely does not make sense to run this test with the
> > aarch64 target... Alexandr, would it make sense to limit this to x86
> > only?
>
> It looks like adding this lines to vm creation fixes all problems with
> other targets on memlock test:
>
> self.set_machine('none')
> self.vm.add_args('-nodefaults')
>
> What's the convenient way to fix it? Resend a new patch?
Hi Alexandr,
Sorry I forgot to CC you. Since the patch in question hasn't been
merged yet, you could send a new revision of the patch and Thomas
could include it in his next pull request. That way the fixed patch
will be introduced in one commit rather than a broken commit followed
by a fix.
Stefan
>
>
> Best regards,
>
> Alexandr
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PULL 00/27] Functional tests, Microblaze endianness & pc/q35 cleanups
2025-06-04 13:11 ` Stefan Hajnoczi
@ 2025-06-04 13:19 ` Thomas Huth
0 siblings, 0 replies; 33+ messages in thread
From: Thomas Huth @ 2025-06-04 13:19 UTC (permalink / raw)
To: Stefan Hajnoczi, Alexandr Moshkov; +Cc: qemu-devel, Stefan Hajnoczi
On 04/06/2025 15.11, Stefan Hajnoczi wrote:
> On Wed, Jun 4, 2025 at 3:51 AM Alexandr Moshkov
> <dtalexundeer@yandex-team.ru> wrote:
>>
>>
>> On 5/29/25 01:12, Thomas Huth wrote:
>>> On 28/05/2025 21.23, Stefan Hajnoczi wrote:
>>>> On Wed, May 28, 2025 at 6:12 AM Thomas Huth <thuth@redhat.com> wrote:
>>>>>
>>>>> Hi!
>>>>>
>>>>> The following changes since commit
>>>>> 80db93b2b88f9b3ed8927ae7ac74ca30e643a83e:
>>>>>
>>>>> Merge tag 'pull-aspeed-20250526' of
>>>>> https://github.com/legoater/qemu into staging (2025-05-26 10:16:59
>>>>> -0400)
>>>>>
>>>>> are available in the Git repository at:
>>>>>
>>>>> https://gitlab.com/thuth/qemu.git tags/pull-request-2025-05-28
>>>>>
>>>>> for you to fetch changes up to
>>>>> 9c2da02e184fddfa7cd7d7813455c2306daae99a:
>>>>>
>>>>> tests/unit/test-util-sockets: fix mem-leak on error object
>>>>> (2025-05-28 11:59:47 +0200)
>>>>>
>>>>> ----------------------------------------------------------------
>>>>> * Functional tests improvements
>>>>> * Endianness improvements/clean-ups for the Microblaze machines
>>>>> * Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and
>>>>> related code
>>>>>
>>>>> ----------------------------------------------------------------
>>>>> Alexandr Moshkov (2):
>>>>> tests/functional: add skipLockedMemoryTest decorator
>>>>> tests/functional: add memlock tests
>>>>
>>>> Hi Thomas and Alexandr,
>>>> The memlock tests are failing:
>>>> https://gitlab.com/qemu-project/qemu/-/jobs/10181084830#L5421
>>>> https://gitlab.com/qemu-project/qemu/-/jobs/10181084865#L5476
>>>>
>>>> Please take a look and send a new pull request. Thanks!
>>>
>> Hello! I think Stefan forgot to CC me in his reply. Only now find this
>> message)
>>
>>
>>> According to the log:
>>>
>>> Output: qemu-system-aarch64: No machine specified, and there is no
>>> default
>>>
>>> I think it likely does not make sense to run this test with the
>>> aarch64 target... Alexandr, would it make sense to limit this to x86
>>> only?
>>
>> It looks like adding this lines to vm creation fixes all problems with
>> other targets on memlock test:
>>
>> self.set_machine('none')
>> self.vm.add_args('-nodefaults')
>>
>> What's the convenient way to fix it? Resend a new patch?
>
> Hi Alexandr,
> Sorry I forgot to CC you. Since the patch in question hasn't been
> merged yet, you could send a new revision of the patch and Thomas
> could include it in his next pull request. That way the fixed patch
> will be introduced in one commit rather than a broken commit followed
> by a fix.
Yes, please send a new version of the patch. Make sure to test with all
targets enabled, or change the hunk in meson.build to include it for the x86
target only. I think I'd even prefer the latter, since otherwise you might
run out of memory easily when doing the tests in parallel with:
"make -j$(nproc) check-functional"
Thanks,
Thomas
^ permalink raw reply [flat|nested] 33+ messages in thread