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Thu, 29 May 2025 04:56:25 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::ce80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4efe5b887sm1853198f8f.18.2025.05.29.04.56.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:56:24 -0700 (PDT) Date: Thu, 29 May 2025 13:56:24 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Fei Wu Subject: Re: [PATCH v3 2/4] target/riscv: Add server platform reference cpu Message-ID: <20250529-9c1e4e13c8dad55fddbd31e3@orel> References: <20250528200129.1548259-1-dbarboza@ventanamicro.com> <20250528200129.1548259-3-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250528200129.1548259-3-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, May 28, 2025 at 05:01:27PM -0300, Daniel Henrique Barboza wrote: > From: Fei Wu > > The harts requirements of RISC-V server platform [1] require RVA23 ISA > profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides > a virt CPU type (rvsp-ref) as compliant as possible. > > [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc > > Signed-off-by: Fei Wu > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 11 +++++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 1ee05eb393..70978fd53c 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -55,6 +55,7 @@ > #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") > #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") > #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu") > +#define TYPE_RISCV_CPU_RVSP_REF RISCV_CPU_TYPE_NAME("rvsp-ref") > #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 4a30cf8444..ec2fbc0e78 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -3166,6 +3166,17 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.max_satp_mode = VM_1_10_SV39, > ), > > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSP_REF, TYPE_RISCV_VENDOR_CPU, > + .misa_mxl_max = MXL_RV64, > + .profile = &RVA23S64, > + > + /* ISA extensions */ > + .cfg.ext_zkr = true, > + .cfg.ext_svadu = true, > + > + .cfg.max_satp_mode = VM_1_10_SV57, This is still missing several extensions required by the platform spec. Sdtrig Sdext Ssccfg Ssstrict Ssaia Thanks, drew > + ), > + > #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, > .cfg.max_satp_mode = VM_1_10_SV57, > -- > 2.49.0 >