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x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.132, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 5 Jun 2025 11:29:59 +0000 Shameerali Kolothum Thodi wrote: > > -----Original Message----- > > From: Igor Mammedov > > Sent: Thursday, June 5, 2025 11:55 AM > > To: Shameer Kolothum via > > Cc: Shameerali Kolothum Thodi > > ; qemu-arm@nongnu.org; > > eric.auger@redhat.com; peter.maydell@linaro.org; jgg@nvidia.com; > > nicolinc@nvidia.com; ddutile@redhat.com; berrange@redhat.com; > > nathanc@nvidia.com; mochs@nvidia.com; smostafa@google.com; Linuxarm > > ; Wangzhou (B) ; > > jiangkunkun ; Jonathan Cameron > > ; zhangfei.gao@linaro.org > > Subject: Re: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root > > Complex association > > > > On Mon, 2 Jun 2025 16:41:05 +0100 > > Shameer Kolothum via wrote: > > > > > Although this change does not affect functionality at present, it is > > > required when we add support for user-creatable SMMUv3 devices in > > > future patches. > > > > > > Signed-off-by: Shameer Kolothum > > > > > --- > > > hw/arm/smmuv3.c | 8 ++++++++ > > > 1 file changed, 8 insertions(+) > > > > > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > > > index ab67972353..7e934336c2 100644 > > > --- a/hw/arm/smmuv3.c > > > +++ b/hw/arm/smmuv3.c > > > @@ -24,6 +24,7 @@ > > > #include "hw/qdev-properties.h" > > > #include "hw/qdev-core.h" > > > #include "hw/pci/pci.h" > > > +#include "hw/pci/pci_bridge.h" > > > #include "cpu.h" > > > #include "exec/target_page.h" > > > #include "trace.h" > > > @@ -1881,6 +1882,13 @@ static void smmu_realize(DeviceState *d, Error > > **errp) > > > SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s); > > > SysBusDevice *dev = SYS_BUS_DEVICE(d); > > > Error *local_err = NULL; > > > + Object *bus; > > > + > > > + bus = object_property_get_link(OBJECT(d), "primary-bus", > > &error_abort); > > I'd replace this with direct field access like in smmu_base_realize > > Ok. > > > in QEMU with PCI, usually we specify bus to attach to with 'bus' property, > > wouldn't it better to rename "primary-bus" to 'bus' to be consistent with > > the rest of PCI code (and before "primary-bus" shows up as a CLI option, > > so far (before this series) it looks like it's an internal property)? > > That was tried in v2 and since SMMUv3 is not a pci device by itself(it is a > sysbus device) reusing the default "bus" property to establish an association > with a PCI bus created problems, > https://lore.kernel.org/qemu-devel/877c2ut0zk.fsf@pond.sub.org/ that was an approach was trying to workaround by patching dc->bus_type, which is obviously wrong. I'm not talking about changing device type or something similar, but about renaming 'primary-bus' property name to 'bus' so it would be consistent interface wise with PCI or other QEMU devices that are attached to a bus. > > > + if (!bus || !object_dynamic_cast(bus->parent, > > TYPE_PCI_HOST_BRIDGE)) { > > Also looking at smmu_base_realize, it has NULL pointer check already. > > Which also rises question, shouldn't smmu_base_realize check for > > TYPE_PCI_HOST_BRIDGE as well (aka can smmu be attached to anything > > else but a host bridge)? > > Not at the moment in Qemu. Though the SMMUv3 specification allows it to > be associated with non-pci devices as well. then perhaps move, the check to smmu_base_realize() for now? if smmu + non-pci ever materialize, it can be refactored at that time. > Thanks, > Shameer >