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From: Igor Mammedov <imammedo@redhat.com>
To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
Cc: Shameer Kolothum via <qemu-devel@nongnu.org>,
	"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	"eric.auger@redhat.com" <eric.auger@redhat.com>,
	"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
	"jgg@nvidia.com" <jgg@nvidia.com>,
	"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
	"ddutile@redhat.com" <ddutile@redhat.com>,
	"berrange@redhat.com" <berrange@redhat.com>,
	"nathanc@nvidia.com" <nathanc@nvidia.com>,
	"mochs@nvidia.com" <mochs@nvidia.com>,
	"smostafa@google.com" <smostafa@google.com>,
	Linuxarm <linuxarm@huawei.com>,
	"Wangzhou (B)" <wangzhou1@hisilicon.com>,
	jiangkunkun <jiangkunkun@huawei.com>,
	"Jonathan Cameron" <jonathan.cameron@huawei.com>,
	"zhangfei.gao@linaro.org" <zhangfei.gao@linaro.org>
Subject: Re: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association
Date: Thu, 5 Jun 2025 15:05:29 +0200	[thread overview]
Message-ID: <20250605150529.0d0cbb8c@imammedo.users.ipa.redhat.com> (raw)
In-Reply-To: <83a0966672fc4785817784dbdf08aef3@huawei.com>

On Thu, 5 Jun 2025 12:36:52 +0000
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> wrote:

> > -----Original Message-----
> > From: Igor Mammedov <imammedo@redhat.com>
> > Sent: Thursday, June 5, 2025 1:20 PM
> > To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> > Cc: Shameer Kolothum via <qemu-devel@nongnu.org>; qemu-
> > arm@nongnu.org; eric.auger@redhat.com; peter.maydell@linaro.org;
> > jgg@nvidia.com; nicolinc@nvidia.com; ddutile@redhat.com;
> > berrange@redhat.com; nathanc@nvidia.com; mochs@nvidia.com;
> > smostafa@google.com; Linuxarm <linuxarm@huawei.com>; Wangzhou (B)
> > <wangzhou1@hisilicon.com>; jiangkunkun <jiangkunkun@huawei.com>;
> > Jonathan Cameron <jonathan.cameron@huawei.com>;
> > zhangfei.gao@linaro.org
> > Subject: Re: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root
> > Complex association  
> 
> [..]
> 
> > > > in QEMU with PCI, usually we specify bus to attach to with 'bus'  
> > property,  
> > > > wouldn't it better to rename "primary-bus" to 'bus' to be consistent  
> > with  
> > > > the rest of PCI code (and before "primary-bus" shows up as a CLI option,
> > > > so far (before this series) it looks like it's an internal property)?  
> > >
> > > That was tried in v2 and since SMMUv3 is not a pci device by itself(it is a
> > > sysbus device) reusing the default "bus" property to establish an  
> > association  
> > > with a PCI bus created problems,
> > > https://lore.kernel.org/qemu-devel/877c2ut0zk.fsf@pond.sub.org/  
> > 
> > that was an approach was trying to workaround by patching dc->bus_type,
> > which is obviously wrong.
> > 
> > I'm not talking about changing device type or something similar,
> > but about renaming 'primary-bus' property name to 'bus'  
> 
> I have tried that earlier and gets this,
> -device arm-smmuv3,bus=pcie.0,id=smmuv3.0: Device 'arm-smmuv3' can't go on PCIE bus
> 
> IIRC, the above mentioned patched dc->bus_type = TYPE_PCIE_BUS was used 
> to avoid that.
> 
> Or am I missing something here?

sigh, but you a right.
qdev_device_add_from_qdict() && co can't handle that without heavy refactoring.

 
> > so it would be consistent interface wise with PCI or other QEMU devices
> > that are attached to a bus.
> >   
> > > > > +    if (!bus || !object_dynamic_cast(bus->parent,  
> > > > TYPE_PCI_HOST_BRIDGE)) {
> > > > Also looking at smmu_base_realize, it has NULL pointer check already.
> > > > Which also rises question, shouldn't smmu_base_realize check for
> > > > TYPE_PCI_HOST_BRIDGE as well (aka can smmu be attached to anything
> > > > else but a host bridge)?  
> > >
> > > Not at the moment in Qemu. Though the SMMUv3 specification allows it  
> > to  
> > > be associated with non-pci devices as well.  
> > 
> > then perhaps move, the check to smmu_base_realize() for now?
> > 
> > if smmu + non-pci ever materialize, it can be refactored at that time.  
> 
> Ok.
> 
> Thanks,
> Shameer
> 



  reply	other threads:[~2025-06-05 13:06 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-02 15:41 [PATCH v3 0/6] hw/arm/virt: Add support for user creatable SMMUv3 device Shameer Kolothum via
2025-06-02 15:41 ` [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association Shameer Kolothum via
2025-06-05  9:13   ` Eric Auger
2025-06-05  9:53   ` Eric Auger
2025-06-05 10:02     ` Eric Auger via
2025-06-05 11:15       ` Shameerali Kolothum Thodi via
2025-06-05 10:55   ` Igor Mammedov
2025-06-05 11:29     ` Shameerali Kolothum Thodi via
2025-06-05 12:19       ` Igor Mammedov
2025-06-05 12:36         ` Shameerali Kolothum Thodi via
2025-06-05 13:05           ` Igor Mammedov [this message]
2025-06-02 15:41 ` [PATCH v3 2/6] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build Shameer Kolothum via
2025-06-05  9:39   ` Eric Auger
2025-06-05 11:10     ` Shameerali Kolothum Thodi via
2025-06-02 15:41 ` [PATCH v3 3/6] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Shameer Kolothum via
2025-06-05  9:57   ` Eric Auger
2025-06-05 11:14     ` Shameerali Kolothum Thodi via
2025-06-02 15:41 ` [PATCH v3 4/6] hw/arm/virt: Factor out common SMMUV3 dt bindings code Shameer Kolothum via
2025-06-02 15:41 ` [PATCH v3 5/6] hw/arm/virt: Add an SMMU_IO_LEN macro Shameer Kolothum via
2025-06-02 15:41 ` [PATCH v3 6/6] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Shameer Kolothum via
2025-06-05 12:45   ` Eric Auger
2025-06-05  2:02 ` [PATCH v3 0/6] hw/arm/virt: Add support for user creatable SMMUv3 device Nathan Chen
2025-06-05  2:34   ` Donald Dutile
2025-06-05 17:58     ` Nathan Chen
2025-06-05 20:58       ` Donald Dutile

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