* [PATCH v8 1/8] ppc/pnv: Introduce Pnv11Chip
2025-06-08 18:28 [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
@ 2025-06-08 18:28 ` Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 2/8] ppc/pnv: Introduce Power11 PowerNV machine Aditya Gupta
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aditya Gupta @ 2025-06-08 18:28 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin
Cc: Harsh Prateek Bora, Mahesh J Salgaonkar, Madhavan Srinivasan,
qemu-devel, qemu-ppc, Frédéric Barrat
Implement Pnv11Chip, currently without chiptod, xive and phb.
Chiptod, XIVE, PHB are implemented in later patches.
Since Power11 core is same as Power10, the implementation of Pnv11Chip
is a duplicate of corresponding Pnv10Chip.
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv.c | 311 +++++++++++++++++++++++++++++++++++++
hw/ppc/pnv_core.c | 17 ++
include/hw/ppc/pnv.h | 20 +++
include/hw/ppc/pnv_chip.h | 7 +
include/hw/ppc/pnv_xscom.h | 49 ++++++
5 files changed, 404 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 4a49e9d1a865..59642d771ebc 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -490,6 +490,33 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
}
+static void pnv_chip_power11_dt_populate(PnvChip *chip, void *fdt)
+{
+ static const char compat[] = "ibm,power11-xscom\0ibm,xscom";
+ int i;
+
+ pnv_dt_xscom(chip, fdt, 0,
+ cpu_to_be64(PNV11_XSCOM_BASE(chip)),
+ cpu_to_be64(PNV11_XSCOM_SIZE),
+ compat, sizeof(compat));
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pnv_core = chip->cores[i];
+ int offset;
+
+ offset = pnv_dt_core(chip, pnv_core, fdt);
+
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_31, sizeof(pa_features_31))));
+ }
+
+ if (chip->ram_size) {
+ pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
+ }
+
+ pnv_dt_lpc(chip, fdt, 0, PNV11_LPCM_BASE(chip), PNV11_LPCM_SIZE);
+}
+
static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
{
uint32_t io_base = d->ioport_id;
@@ -822,6 +849,26 @@ static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
return pnv_lpc_isa_create(&chip10->lpc, false, errp);
}
+static ISABus *pnv_chip_power11_isa_create(PnvChip *chip, Error **errp)
+{
+ Pnv11Chip *chip11 = PNV11_CHIP(chip);
+ qemu_irq irq;
+
+ irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPCHC);
+ qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "LPCHC", 0, irq);
+
+ irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ0);
+ qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 0, irq);
+ irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ1);
+ qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 1, irq);
+ irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ2);
+ qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 2, irq);
+ irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ3);
+ qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 3, irq);
+
+ return pnv_lpc_isa_create(&chip11->lpc, false, errp);
+}
+
static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
{
return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
@@ -885,6 +932,12 @@ static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
return PNV10_XSCOM_EC_BASE(core_id);
}
+static uint64_t pnv_chip_power11_xscom_core_base(PnvChip *chip,
+ uint32_t core_id)
+{
+ return PNV11_XSCOM_EC_BASE(core_id);
+}
+
static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
{
PowerPCCPUClass *ppc_default =
@@ -914,6 +967,13 @@ static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf)
pnv_chip_power9_pic_print_info_child, buf);
}
+static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf)
+{
+ Pnv11Chip *chip11 = PNV11_CHIP(chip);
+
+ pnv_psi_pic_print_info(&chip11->psi, buf);
+}
+
/* Always give the first 1GB to chip 0 else we won't boot */
static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
{
@@ -1451,6 +1511,8 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
#define POWER10_CORE_MASK (0xffffffffffffffull)
+#define POWER11_CORE_MASK (0xffffffffffffffull)
+
static void pnv_chip_power8_instance_init(Object *obj)
{
Pnv8Chip *chip8 = PNV8_CHIP(obj);
@@ -2264,6 +2326,208 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
}
}
+static void pnv_chip_power11_instance_init(Object *obj)
+{
+ Pnv11Chip *chip11 = PNV11_CHIP(obj);
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
+ int i;
+
+ object_initialize_child(obj, "adu", &chip11->adu, TYPE_PNV_ADU);
+
+ /*
+ * Use Power10 device models for PSI/LPC/OCC/SBE/HOMER as corresponding
+ * device models for Power11 are same
+ */
+ object_initialize_child(obj, "psi", &chip11->psi, TYPE_PNV10_PSI);
+ object_initialize_child(obj, "lpc", &chip11->lpc, TYPE_PNV10_LPC);
+ object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV10_OCC);
+ object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV10_SBE);
+ object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV10_HOMER);
+ object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
+ TYPE_PNV_N1_CHIPLET);
+
+ for (i = 0; i < pcc->i2c_num_engines; i++) {
+ object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I2C);
+ }
+
+ for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
+ object_initialize_child(obj, "pib_spic[*]", &chip11->pib_spic[i],
+ TYPE_PNV_SPI);
+ }
+}
+
+static void pnv_chip_power11_quad_realize(Pnv11Chip *chip11, Error **errp)
+{
+ PnvChip *chip = PNV_CHIP(chip11);
+ int i;
+
+ chip11->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
+ chip11->quads = g_new0(PnvQuad, chip11->nr_quads);
+
+ for (i = 0; i < chip11->nr_quads; i++) {
+ PnvQuad *eq = &chip11->quads[i];
+
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
+ PNV_QUAD_TYPE_NAME("power11"));
+
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_EQ_BASE(eq->quad_id),
+ &eq->xscom_regs);
+
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_QME_BASE(eq->quad_id),
+ &eq->xscom_qme_regs);
+ }
+}
+
+static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
+{
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
+ PnvChip *chip = PNV_CHIP(dev);
+ Pnv11Chip *chip11 = PNV11_CHIP(dev);
+ Error *local_err = NULL;
+ int i;
+
+ /* XSCOM bridge is first */
+ pnv_xscom_init(chip, PNV11_XSCOM_SIZE, PNV11_XSCOM_BASE(chip));
+
+ pcc->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ /* ADU */
+ object_property_set_link(OBJECT(&chip11->adu), "lpc", OBJECT(&chip11->lpc),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&chip11->adu), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_ADU_BASE,
+ &chip11->adu.xscom_regs);
+
+ pnv_chip_power11_quad_realize(chip11, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ /* WIP: XIVE added in future patch */
+
+ /* Processor Service Interface (PSI) Host Bridge */
+ object_property_set_int(OBJECT(&chip11->psi), "bar",
+ PNV11_PSIHB_BASE(chip), &error_fatal);
+ if (!qdev_realize(DEVICE(&chip11->psi), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_PSIHB_BASE,
+ &PNV_PSI(&chip11->psi)->xscom_regs);
+
+ /* LPC */
+ if (!qdev_realize(DEVICE(&chip11->lpc), NULL, errp)) {
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), PNV11_LPCM_BASE(chip),
+ &chip11->lpc.xscom_regs);
+
+ chip->fw_mr = &chip11->lpc.isa_fw;
+ chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
+ (uint64_t) PNV11_LPCM_BASE(chip));
+
+ /* HOMER (must be created before OCC) */
+ object_property_set_link(OBJECT(&chip11->homer), "chip", OBJECT(chip),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&chip11->homer), NULL, errp)) {
+ return;
+ }
+ /* Homer Xscom region */
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_PBA_BASE,
+ &chip11->homer.pba_regs);
+ /* Homer RAM region */
+ memory_region_add_subregion(get_system_memory(), chip11->homer.base,
+ &chip11->homer.mem);
+
+ /* Create the simplified OCC model */
+ object_property_set_link(OBJECT(&chip11->occ), "homer",
+ OBJECT(&chip11->homer), &error_abort);
+ if (!qdev_realize(DEVICE(&chip11->occ), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_OCC_BASE,
+ &chip11->occ.xscom_regs);
+ qdev_connect_gpio_out(DEVICE(&chip11->occ), 0, qdev_get_gpio_in(
+ DEVICE(&chip11->psi), PSIHB9_IRQ_OCC));
+
+ /* OCC SRAM model */
+ memory_region_add_subregion(get_system_memory(),
+ PNV11_OCC_SENSOR_BASE(chip),
+ &chip11->occ.sram_regs);
+
+ /* SBE */
+ if (!qdev_realize(DEVICE(&chip11->sbe), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_SBE_CTRL_BASE,
+ &chip11->sbe.xscom_ctrl_regs);
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_SBE_MBOX_BASE,
+ &chip11->sbe.xscom_mbox_regs);
+ qdev_connect_gpio_out(DEVICE(&chip11->sbe), 0, qdev_get_gpio_in(
+ DEVICE(&chip11->psi), PSIHB9_IRQ_PSU));
+
+ /* N1 chiplet */
+ if (!qdev_realize(DEVICE(&chip11->n1_chiplet), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_CHIPLET_CTRL_REGS_BASE,
+ &chip11->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr);
+
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_EQ_BASE,
+ &chip11->n1_chiplet.xscom_pb_eq_mr);
+
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_ES_BASE,
+ &chip11->n1_chiplet.xscom_pb_es_mr);
+
+ /* WIP: PHB added in future patch */
+
+ /*
+ * I2C
+ */
+ for (i = 0; i < pcc->i2c_num_engines; i++) {
+ Object *obj = OBJECT(&chip11->i2c[i]);
+
+ object_property_set_int(obj, "engine", i + 1, &error_fatal);
+ object_property_set_int(obj, "num-busses",
+ pcc->i2c_ports_per_engine[i],
+ &error_fatal);
+ object_property_set_link(obj, "chip", OBJECT(chip), &error_abort);
+ if (!qdev_realize(DEVICE(obj), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_I2CM_BASE +
+ (chip11->i2c[i].engine - 1) *
+ PNV11_XSCOM_I2CM_SIZE,
+ &chip11->i2c[i].xscom_regs);
+ qdev_connect_gpio_out(DEVICE(&chip11->i2c[i]), 0,
+ qdev_get_gpio_in(DEVICE(&chip11->psi),
+ PSIHB9_IRQ_SBE_I2C));
+ }
+ /* PIB SPI Controller */
+ for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
+ object_property_set_int(OBJECT(&chip11->pib_spic[i]), "spic_num",
+ i, &error_fatal);
+ /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */
+ object_property_set_int(OBJECT(&chip11->pib_spic[i]), "transfer_len",
+ (i == 2) ? 1 : 4, &error_fatal);
+ object_property_set_int(OBJECT(&chip11->pib_spic[i]), "chip-id",
+ chip->chip_id, &error_fatal);
+ if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT
+ (&chip11->pib_spic[i])), errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_PIB_SPIC_BASE +
+ i * PNV11_XSCOM_PIB_SPIC_SIZE,
+ &chip11->pib_spic[i].xscom_spic_regs);
+ }
+}
+
static void pnv_rainier_i2c_init(PnvMachineState *pnv)
{
int i;
@@ -2329,6 +2593,35 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, const void *data)
&k->parent_realize);
}
+static uint32_t pnv_chip_power11_xscom_pcba(PnvChip *chip, uint64_t addr)
+{
+ addr &= (PNV11_XSCOM_SIZE - 1);
+ return addr >> 3;
+}
+
+static void pnv_chip_power11_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PnvChipClass *k = PNV_CHIP_CLASS(klass);
+
+ static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
+
+ k->chip_cfam_id = 0x220da04980000000ull; /* P11 DD2.0 (with NX) */
+ k->cores_mask = POWER11_CORE_MASK;
+ k->get_pir_tir = pnv_get_pir_tir_p10;
+ k->isa_create = pnv_chip_power11_isa_create;
+ k->dt_populate = pnv_chip_power11_dt_populate;
+ k->pic_print_info = pnv_chip_power11_pic_print_info;
+ k->xscom_core_base = pnv_chip_power11_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power11_xscom_pcba;
+ dc->desc = "PowerNV Chip Power11";
+ k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
+ k->i2c_ports_per_engine = i2c_ports_per_engine;
+
+ device_class_set_parent_realize(dc, pnv_chip_power11_realize,
+ &k->parent_realize);
+}
+
static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip,
Error **errp)
{
@@ -2963,6 +3256,13 @@ static void pnv_machine_class_init(ObjectClass *oc, const void *data)
.parent = TYPE_PNV10_CHIP, \
}
+#define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \
+ { \
+ .name = type, \
+ .class_init = class_initfn, \
+ .parent = TYPE_PNV11_CHIP, \
+ }
+
static const TypeInfo types[] = {
{
.name = MACHINE_TYPE_NAME("powernv10-rainier"),
@@ -3018,6 +3318,17 @@ static const TypeInfo types[] = {
.abstract = true,
},
+ /*
+ * P11 chip and variants
+ */
+ {
+ .name = TYPE_PNV11_CHIP,
+ .parent = TYPE_PNV_CHIP,
+ .instance_init = pnv_chip_power11_instance_init,
+ .instance_size = sizeof(Pnv11Chip),
+ },
+ DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_init),
+
/*
* P10 chip and variants
*/
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 08c20224b97d..fb2dfc7ba212 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -473,6 +473,11 @@ static void pnv_core_power10_class_init(ObjectClass *oc, const void *data)
pcc->xscom_size = PNV10_XSCOM_EC_SIZE;
}
+static void pnv_core_power11_class_init(ObjectClass *oc, const void *data)
+{
+ pnv_core_power10_class_init(oc, data);
+}
+
static void pnv_core_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -504,6 +509,7 @@ static const TypeInfo pnv_core_infos[] = {
DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"),
DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
+ DEFINE_PNV_CORE_TYPE(power11, "power11_v2.0"),
};
DEFINE_TYPES(pnv_core_infos)
@@ -725,6 +731,12 @@ static void pnv_quad_power10_class_init(ObjectClass *oc, const void *data)
pqc->xscom_qme_size = PNV10_XSCOM_QME_SIZE;
}
+static void pnv_quad_power11_class_init(ObjectClass *oc, const void *data)
+{
+ /* Power11 quad is similar to Power10 quad */
+ pnv_quad_power10_class_init(oc, data);
+}
+
static void pnv_quad_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -752,6 +764,11 @@ static const TypeInfo pnv_quad_infos[] = {
.name = PNV_QUAD_TYPE_NAME("power10"),
.class_init = pnv_quad_power10_class_init,
},
+ {
+ .parent = TYPE_PNV_QUAD,
+ .name = PNV_QUAD_TYPE_NAME("power11"),
+ .class_init = pnv_quad_power11_class_init,
+ },
};
DEFINE_TYPES(pnv_quad_infos);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index d8fca079f2fe..f0002627bcab 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -33,6 +33,7 @@ typedef struct PnvChip PnvChip;
typedef struct Pnv8Chip Pnv8Chip;
typedef struct Pnv9Chip Pnv9Chip;
typedef struct Pnv10Chip Pnv10Chip;
+typedef struct Pnv10Chip Pnv11Chip;
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
@@ -57,6 +58,10 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
+#define TYPE_PNV_CHIP_POWER11 PNV_CHIP_TYPE_NAME("power11_v2.0")
+DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER11,
+ TYPE_PNV_CHIP_POWER11)
+
PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id);
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
@@ -252,4 +257,19 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
#define PNV10_HOMER_BASE(chip) \
(0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
+/* Power11 */
+#define PNV11_XSCOM_SIZE PNV10_XSCOM_SIZE
+#define PNV11_XSCOM_BASE(chip) PNV10_XSCOM_BASE(chip)
+
+#define PNV11_LPCM_SIZE PNV10_LPCM_SIZE
+#define PNV11_LPCM_BASE(chip) PNV10_LPCM_BASE(chip)
+
+#define PNV11_PSIHB_ESB_SIZE PNV10_PSIHB_ESB_SIZE
+#define PNV11_PSIHB_ESB_BASE(chip) PNV10_PSIHB_ESB_BASE(chip)
+
+#define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE
+#define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip)
+
+#define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip)
+
#endif /* PPC_PNV_H */
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 24ce37a9c8e4..6bd930f8b439 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -141,6 +141,13 @@ struct Pnv10Chip {
#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
#define PNV10_PIR2THREAD(pir) (((pir) & 0x7f))
+#define TYPE_PNV11_CHIP "pnv11-chip"
+DECLARE_INSTANCE_CHECKER(Pnv11Chip, PNV11_CHIP,
+ TYPE_PNV11_CHIP)
+
+/* Power11 core is same as Power10 */
+typedef struct Pnv10Chip Pnv11Chip;
+
struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index b14549db7033..610b075a27c3 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -207,6 +207,55 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_PIB_SPIC_BASE 0xc0000
#define PNV10_XSCOM_PIB_SPIC_SIZE 0x20
+/*
+ * Power11 core is same as Power10
+ */
+#define PNV11_XSCOM_EC_BASE(core) PNV10_XSCOM_EC_BASE(core)
+
+#define PNV11_XSCOM_ADU_BASE PNV10_XSCOM_ADU_BASE
+#define PNV11_XSCOM_ADU_SIZE PNV10_XSCOM_ADU_SIZE
+
+#define PNV11_XSCOM_QME_BASE(core) PNV10_XSCOM_QME_BASE(core)
+
+#define PNV11_XSCOM_EQ_BASE(core) PNV10_XSCOM_EQ_BASE(core)
+
+#define PNV11_XSCOM_PSIHB_BASE PNV10_XSCOM_PSIHB_BASE
+#define PNV11_XSCOM_PSIHB_SIZE PNV10_XSCOM_PSIHB_SIZE
+
+#define PNV11_XSCOM_I2CM_BASE PNV10_XSCOM_I2CM_BASE
+#define PNV11_XSCOM_I2CM_SIZE PNV10_XSCOM_I2CM_SIZE
+
+#define PNV11_XSCOM_CHIPTOD_BASE PNV10_XSCOM_CHIPTOD_BASE
+#define PNV11_XSCOM_CHIPTOD_SIZE PNV10_XSCOM_CHIPTOD_SIZE
+
+#define PNV11_XSCOM_OCC_BASE PNV10_XSCOM_OCC_BASE
+#define PNV11_XSCOM_OCC_SIZE PNV10_XSCOM_OCC_SIZE
+
+#define PNV11_XSCOM_SBE_CTRL_BASE PNV10_XSCOM_SBE_CTRL_BASE
+#define PNV11_XSCOM_SBE_CTRL_SIZE PNV10_XSCOM_SBE_CTRL_SIZE
+
+#define PNV11_XSCOM_SBE_MBOX_BASE PNV10_XSCOM_SBE_MBOX_BASE
+#define PNV11_XSCOM_SBE_MBOX_SIZE PNV10_XSCOM_SBE_MBOX_SIZE
+
+#define PNV11_XSCOM_PBA_BASE PNV10_XSCOM_PBA_BASE
+#define PNV11_XSCOM_PBA_SIZE PNV10_XSCOM_PBA_SIZE
+
+#define PNV11_XSCOM_XIVE2_BASE PNV10_XSCOM_XIVE2_BASE
+#define PNV11_XSCOM_XIVE2_SIZE PNV10_XSCOM_XIVE2_SIZE
+
+#define PNV11_XSCOM_N1_CHIPLET_CTRL_REGS_BASE \
+ PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE
+#define PNV11_XSCOM_CHIPLET_CTRL_REGS_SIZE PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE
+
+#define PNV11_XSCOM_N1_PB_SCOM_EQ_BASE PNV10_XSCOM_N1_PB_SCOM_EQ_BASE
+#define PNV11_XSCOM_N1_PB_SCOM_EQ_SIZE PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE
+
+#define PNV11_XSCOM_N1_PB_SCOM_ES_BASE PNV10_XSCOM_N1_PB_SCOM_ES_BASE
+#define PNV11_XSCOM_N1_PB_SCOM_ES_SIZE PNV10_XSCOM_N1_PB_SCOM_ES_SIZE
+
+#define PNV11_XSCOM_PIB_SPIC_BASE PNV10_XSCOM_PIB_SPIC_BASE
+#define PNV11_XSCOM_PIB_SPIC_SIZE PNV10_XSCOM_PIB_SPIC_SIZE
+
void pnv_xscom_init(PnvChip *chip, uint64_t size, hwaddr addr);
int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
uint64_t xscom_base, uint64_t xscom_size,
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v8 2/8] ppc/pnv: Introduce Power11 PowerNV machine
2025-06-08 18:28 [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 1/8] ppc/pnv: Introduce Pnv11Chip Aditya Gupta
@ 2025-06-08 18:28 ` Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 3/8] ppc/pnv: Add XIVE2 controller to Power11 Aditya Gupta
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aditya Gupta @ 2025-06-08 18:28 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin
Cc: Harsh Prateek Bora, Mahesh J Salgaonkar, Madhavan Srinivasan,
qemu-devel, qemu-ppc, Frédéric Barrat
The Powernv11 machine doesn't have XIVE & PHBs as of now
XIVE2 interface and PHB5 added in later patches to Powernv11 machine
Also add mention of Power11 to powernv documentation
Note: A difference from P10's and P11's machine_class_init is, in P11
different number of PHBs cannot be used on the command line, ie. the
following line does NOT exist in pnv_machine_power11_class_init, which
existed in case of Power10:
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
docs/system/ppc/powernv.rst | 9 +++++----
hw/ppc/pnv.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
index f3ec2cc69c0d..5154794cc8cd 100644
--- a/docs/system/ppc/powernv.rst
+++ b/docs/system/ppc/powernv.rst
@@ -1,5 +1,5 @@
-PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
-==================================================================
+PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powernv11``)
+================================================================================
PowerNV (as Non-Virtualized) is the "bare metal" platform using the
OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
@@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today.
Supported devices
-----------------
- * Multi processor support for POWER8, POWER8NVL and POWER9.
+ * Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Power11.
* XSCOM, serial communication sideband bus to configure chiplets.
* Simple LPC Controller.
* Processor Service Interface (PSI) Controller.
- * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
+ * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
+ Power11).
* POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
* Simple OCC is an on-chip micro-controller used for power management tasks.
* iBT device to handle BMC communication, with the internal BMC simulator
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 59642d771ebc..5205728d3329 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -3151,6 +3151,35 @@ static void pnv_machine_p10_rainier_class_init(ObjectClass *oc,
pmc->i2c_init = pnv_rainier_i2c_init;
}
+static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+ static const char compat[] = "qemu,powernv11\0ibm,powernv";
+
+ pmc->compat = compat;
+ pmc->compat_size = sizeof(compat);
+ pmc->max_smt_threads = 4;
+ pmc->has_lpar_per_thread = true;
+ pmc->quirk_tb_big_core = true;
+ pmc->dt_power_mgt = pnv_dt_power_mgt;
+
+ mc->desc = "IBM PowerNV (Non-Virtualized) Power11";
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11_v2.0");
+
+ object_class_property_add_bool(oc, "big-core",
+ pnv_machine_get_big_core,
+ pnv_machine_set_big_core);
+ object_class_property_set_description(oc, "big-core",
+ "Use big-core (aka fused-core) mode");
+
+ object_class_property_add_bool(oc, "lpar-per-core",
+ pnv_machine_get_lpar_per_core,
+ pnv_machine_set_lpar_per_core);
+ object_class_property_set_description(oc, "lpar-per-core",
+ "Use 1 LPAR per core mode");
+}
+
static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
CPUPPCState *env = cpu_env(cs);
@@ -3264,6 +3293,11 @@ static void pnv_machine_class_init(ObjectClass *oc, const void *data)
}
static const TypeInfo types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("powernv11"),
+ .parent = TYPE_PNV_MACHINE,
+ .class_init = pnv_machine_power11_class_init,
+ },
{
.name = MACHINE_TYPE_NAME("powernv10-rainier"),
.parent = MACHINE_TYPE_NAME("powernv10"),
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v8 3/8] ppc/pnv: Add XIVE2 controller to Power11
2025-06-08 18:28 [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 1/8] ppc/pnv: Introduce Pnv11Chip Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 2/8] ppc/pnv: Introduce Power11 PowerNV machine Aditya Gupta
@ 2025-06-08 18:28 ` Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 4/8] ppc/pnv: Add PHB5 PCIe Host bridge " Aditya Gupta
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aditya Gupta @ 2025-06-08 18:28 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin
Cc: Harsh Prateek Bora, Mahesh J Salgaonkar, Madhavan Srinivasan,
qemu-devel, qemu-ppc, Frédéric Barrat
Add a XIVE2 controller to Power11 chip and machine.
The controller has the same logic as Power10.
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv.c | 133 ++++++++++++++++++++++++++++++++++++++++++-
include/hw/ppc/pnv.h | 18 ++++++
2 files changed, 150 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 5205728d3329..cd85278baf53 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -972,6 +972,7 @@ static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf)
Pnv11Chip *chip11 = PNV11_CHIP(chip);
pnv_psi_pic_print_info(&chip11->psi, buf);
+ pnv_xive2_pic_print_info(&chip11->xive, buf);
}
/* Always give the first 1GB to chip 0 else we won't boot */
@@ -1481,6 +1482,50 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
}
+static void pnv_chip_power11_intc_create(PnvChip *chip, PowerPCCPU *cpu,
+ Error **errp)
+{
+ Pnv11Chip *chip11 = PNV11_CHIP(chip);
+ Error *local_err = NULL;
+ Object *obj;
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+ /*
+ * The core creates its interrupt presenter but the XIVE2 interrupt
+ * controller object is initialized afterwards. Hopefully, it's
+ * only used at runtime.
+ */
+ obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip11->xive),
+ &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ pnv_cpu->intc = obj;
+}
+
+static void pnv_chip_power11_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
+{
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+ xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
+}
+
+static void pnv_chip_power11_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
+{
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+ xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
+ pnv_cpu->intc = NULL;
+}
+
+static void pnv_chip_power11_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
+ GString *buf)
+{
+ xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf);
+}
+
/*
* Allowed core identifiers on a POWER8 Processor Chip :
*
@@ -2343,6 +2388,10 @@ static void pnv_chip_power11_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV10_OCC);
object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV10_SBE);
object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV10_HOMER);
+
+ object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2);
+ object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive),
+ "xive-fabric");
object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
TYPE_PNV_N1_CHIPLET);
@@ -2410,11 +2459,33 @@ static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
return;
}
- /* WIP: XIVE added in future patch */
+ /* XIVE2 interrupt controller */
+ object_property_set_int(OBJECT(&chip11->xive), "ic-bar",
+ PNV11_XIVE2_IC_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "esb-bar",
+ PNV11_XIVE2_ESB_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "end-bar",
+ PNV11_XIVE2_END_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "nvpg-bar",
+ PNV11_XIVE2_NVPG_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "nvc-bar",
+ PNV11_XIVE2_NVC_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip11->xive), "tm-bar",
+ PNV11_XIVE2_TM_BASE(chip), &error_fatal);
+ object_property_set_link(OBJECT(&chip11->xive), "chip", OBJECT(chip),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&chip11->xive), errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_XIVE2_BASE,
+ &chip11->xive.xscom_regs);
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip11->psi), "bar",
PNV11_PSIHB_BASE(chip), &error_fatal);
+ /* PSI can be configured to use 64k ESB pages on POWER11 */
+ object_property_set_int(OBJECT(&chip11->psi), "shift", XIVE_ESB_64K,
+ &error_fatal);
if (!qdev_realize(DEVICE(&chip11->psi), NULL, errp)) {
return;
}
@@ -2609,6 +2680,10 @@ static void pnv_chip_power11_class_init(ObjectClass *klass, const void *data)
k->chip_cfam_id = 0x220da04980000000ull; /* P11 DD2.0 (with NX) */
k->cores_mask = POWER11_CORE_MASK;
k->get_pir_tir = pnv_get_pir_tir_p10;
+ k->intc_create = pnv_chip_power11_intc_create;
+ k->intc_reset = pnv_chip_power11_intc_reset;
+ k->intc_destroy = pnv_chip_power11_intc_destroy;
+ k->intc_print_info = pnv_chip_power11_intc_print_info;
k->isa_create = pnv_chip_power11_isa_create;
k->dt_populate = pnv_chip_power11_dt_populate;
k->pic_print_info = pnv_chip_power11_pic_print_info;
@@ -2977,6 +3052,54 @@ static int pnv10_xive_broadcast(XiveFabric *xfb,
return 0;
}
+static int pnv11_xive_match_nvt(XiveFabric *xfb, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool crowd, bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv,
+ XiveTCTXMatch *match)
+{
+ PnvMachineState *pnv = PNV_MACHINE(xfb);
+ int total_count = 0;
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
+ XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+ int count;
+
+ count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd,
+ cam_ignore, priority, logic_serv, match);
+
+ if (count < 0) {
+ return count;
+ }
+
+ total_count += count;
+ }
+
+ return total_count;
+}
+
+static int pnv11_xive_broadcast(XiveFabric *xfb,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool crowd, bool cam_ignore,
+ uint8_t priority)
+{
+ PnvMachineState *pnv = PNV_MACHINE(xfb);
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
+ XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+
+ xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority);
+ }
+ return 0;
+}
+
+
static bool pnv_machine_get_big_core(Object *obj, Error **errp)
{
PnvMachineState *pnv = PNV_MACHINE(obj);
@@ -3155,6 +3278,7 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+ XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
static const char compat[] = "qemu,powernv11\0ibm,powernv";
pmc->compat = compat;
@@ -3164,6 +3288,9 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
pmc->quirk_tb_big_core = true;
pmc->dt_power_mgt = pnv_dt_power_mgt;
+ xfc->match_nvt = pnv11_xive_match_nvt;
+ xfc->broadcast = pnv11_xive_broadcast;
+
mc->desc = "IBM PowerNV (Non-Virtualized) Power11";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11_v2.0");
@@ -3297,6 +3424,10 @@ static const TypeInfo types[] = {
.name = MACHINE_TYPE_NAME("powernv11"),
.parent = TYPE_PNV_MACHINE,
.class_init = pnv_machine_power11_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XIVE_FABRIC },
+ { },
+ },
},
{
.name = MACHINE_TYPE_NAME("powernv10-rainier"),
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index f0002627bcab..cbdddfc73cd4 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -270,6 +270,24 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
#define PNV11_PSIHB_SIZE PNV10_PSIHB_SIZE
#define PNV11_PSIHB_BASE(chip) PNV10_PSIHB_BASE(chip)
+#define PNV11_XIVE2_IC_SIZE PNV10_XIVE2_IC_SIZE
+#define PNV11_XIVE2_IC_BASE(chip) PNV10_XIVE2_IC_BASE(chip)
+
+#define PNV11_XIVE2_TM_SIZE PNV10_XIVE2_TM_SIZE
+#define PNV11_XIVE2_TM_BASE(chip) PNV10_XIVE2_TM_BASE(chip)
+
+#define PNV11_XIVE2_NVC_SIZE PNV10_XIVE2_NVC_SIZE
+#define PNV11_XIVE2_NVC_BASE(chip) PNV10_XIVE2_NVC_BASE(chip)
+
+#define PNV11_XIVE2_NVPG_SIZE PNV10_XIVE2_NVPG_SIZE
+#define PNV11_XIVE2_NVPG_BASE(chip) PNV10_XIVE2_NVPG_BASE(chip)
+
+#define PNV11_XIVE2_ESB_SIZE PNV10_XIVE2_ESB_SIZE
+#define PNV11_XIVE2_ESB_BASE(chip) PNV10_XIVE2_ESB_BASE(chip)
+
+#define PNV11_XIVE2_END_SIZE PNV10_XIVE2_END_SIZE
+#define PNV11_XIVE2_END_BASE(chip) PNV10_XIVE2_END_BASE(chip)
+
#define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip)
#endif /* PPC_PNV_H */
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v8 4/8] ppc/pnv: Add PHB5 PCIe Host bridge to Power11
2025-06-08 18:28 [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
` (2 preceding siblings ...)
2025-06-08 18:28 ` [PATCH v8 3/8] ppc/pnv: Add XIVE2 controller to Power11 Aditya Gupta
@ 2025-06-08 18:28 ` Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 5/8] ppc/pnv: Add ChipTOD model for Power11 Aditya Gupta
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aditya Gupta @ 2025-06-08 18:28 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin
Cc: Harsh Prateek Bora, Mahesh J Salgaonkar, Madhavan Srinivasan,
qemu-devel, qemu-ppc, Frédéric Barrat
Power11 also uses PHB5, same as Power10.
Add Power11 PHBs with similar code as the corresponding Power10 implementation.
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index cd85278baf53..8b0133cecf41 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -973,6 +973,8 @@ static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf)
pnv_psi_pic_print_info(&chip11->psi, buf);
pnv_xive2_pic_print_info(&chip11->xive, buf);
+ object_child_foreach_recursive(OBJECT(chip),
+ pnv_chip_power9_pic_print_info_child, buf);
}
/* Always give the first 1GB to chip 0 else we won't boot */
@@ -2373,6 +2375,7 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
static void pnv_chip_power11_instance_init(Object *obj)
{
+ PnvChip *chip = PNV_CHIP(obj);
Pnv11Chip *chip11 = PNV11_CHIP(obj);
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
int i;
@@ -2395,6 +2398,13 @@ static void pnv_chip_power11_instance_init(Object *obj)
object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
TYPE_PNV_N1_CHIPLET);
+ chip->num_pecs = pcc->num_pecs;
+
+ for (i = 0; i < chip->num_pecs; i++) {
+ object_initialize_child(obj, "pec[*]", &chip11->pecs[i],
+ TYPE_PNV_PHB5_PEC);
+ }
+
for (i = 0; i < pcc->i2c_num_engines; i++) {
object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I2C);
}
@@ -2427,6 +2437,38 @@ static void pnv_chip_power11_quad_realize(Pnv11Chip *chip11, Error **errp)
}
}
+static void pnv_chip_power11_phb_realize(PnvChip *chip, Error **errp)
+{
+ Pnv11Chip *chip11 = PNV11_CHIP(chip);
+ int i;
+
+ for (i = 0; i < chip->num_pecs; i++) {
+ PnvPhb4PecState *pec = &chip11->pecs[i];
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
+ uint32_t pec_cplt_base;
+ uint32_t pec_nest_base;
+ uint32_t pec_pci_base;
+
+ object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
+ object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
+ &error_fatal);
+ object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
+ &error_fatal);
+ if (!qdev_realize(DEVICE(pec), NULL, errp)) {
+ return;
+ }
+
+ pec_cplt_base = pecc->xscom_cplt_base(pec);
+ pec_nest_base = pecc->xscom_nest_base(pec);
+ pec_pci_base = pecc->xscom_pci_base(pec);
+
+ pnv_xscom_add_subregion(chip, pec_cplt_base,
+ &pec->nest_pervasive.xscom_ctrl_regs_mr);
+ pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
+ pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
+ }
+}
+
static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
@@ -2556,7 +2598,12 @@ static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_ES_BASE,
&chip11->n1_chiplet.xscom_pb_es_mr);
- /* WIP: PHB added in future patch */
+ /* PHBs */
+ pnv_chip_power11_phb_realize(chip, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
/*
* I2C
@@ -2690,6 +2737,7 @@ static void pnv_chip_power11_class_init(ObjectClass *klass, const void *data)
k->xscom_core_base = pnv_chip_power11_xscom_core_base;
k->xscom_pcba = pnv_chip_power11_xscom_pcba;
dc->desc = "PowerNV Chip Power11";
+ k->num_pecs = PNV10_CHIP_MAX_PEC;
k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
k->i2c_ports_per_engine = i2c_ports_per_engine;
@@ -3281,6 +3329,13 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
static const char compat[] = "qemu,powernv11\0ibm,powernv";
+ static GlobalProperty phb_compat[] = {
+ { TYPE_PNV_PHB, "version", "5" },
+ { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
+ };
+
+ compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
+
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->max_smt_threads = 4;
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v8 5/8] ppc/pnv: Add ChipTOD model for Power11
2025-06-08 18:28 [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
` (3 preceding siblings ...)
2025-06-08 18:28 ` [PATCH v8 4/8] ppc/pnv: Add PHB5 PCIe Host bridge " Aditya Gupta
@ 2025-06-08 18:28 ` Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 6/8] tests/powernv: Switch to buildroot images instead of op-build Aditya Gupta
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aditya Gupta @ 2025-06-08 18:28 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin
Cc: Harsh Prateek Bora, Mahesh J Salgaonkar, Madhavan Srinivasan,
qemu-devel, qemu-ppc, Cédric Le Goater,
Frédéric Barrat
Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod
code as the Power11 core is same as Power10 core.
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv.c | 15 +++++++++
hw/ppc/pnv_chiptod.c | 59 ++++++++++++++++++++++++++++++++++++
include/hw/ppc/pnv_chiptod.h | 2 ++
3 files changed, 76 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 8b0133cecf41..b5523bab3803 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2395,6 +2395,8 @@ static void pnv_chip_power11_instance_init(Object *obj)
object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2);
object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive),
"xive-fabric");
+ object_initialize_child(obj, "chiptod", &chip11->chiptod,
+ TYPE_PNV11_CHIPTOD);
object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
TYPE_PNV_N1_CHIPLET);
@@ -2545,6 +2547,19 @@ static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
(uint64_t) PNV11_LPCM_BASE(chip));
+ /* ChipTOD */
+ object_property_set_bool(OBJECT(&chip11->chiptod), "primary",
+ chip->chip_id == 0, &error_abort);
+ object_property_set_bool(OBJECT(&chip11->chiptod), "secondary",
+ chip->chip_id == 1, &error_abort);
+ object_property_set_link(OBJECT(&chip11->chiptod), "chip", OBJECT(chip),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&chip11->chiptod), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV11_XSCOM_CHIPTOD_BASE,
+ &chip11->chiptod.xscom_regs);
+
/* HOMER (must be created before OCC) */
object_property_set_link(OBJECT(&chip11->homer), "chip", OBJECT(chip),
&error_abort);
diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
index b9e9c7ba3dbb..f887a18cde8d 100644
--- a/hw/ppc/pnv_chiptod.c
+++ b/hw/ppc/pnv_chiptod.c
@@ -210,6 +210,22 @@ static void chiptod_power10_broadcast_ttype(PnvChipTOD *sender,
}
}
+static void chiptod_power11_broadcast_ttype(PnvChipTOD *sender,
+ uint32_t trigger)
+{
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]);
+ PnvChipTOD *chiptod = &chip11->chiptod;
+
+ if (chiptod != sender) {
+ chiptod_receive_ttype(chiptod, trigger);
+ }
+ }
+}
+
static PnvCore *pnv_chip_get_core_by_xscom_base(PnvChip *chip,
uint32_t xscom_base)
{
@@ -283,6 +299,12 @@ static PnvCore *chiptod_power10_tx_ttype_target(PnvChipTOD *chiptod,
}
}
+static PnvCore *chiptod_power11_tx_ttype_target(PnvChipTOD *chiptod,
+ uint64_t val)
+{
+ return chiptod_power10_tx_ttype_target(chiptod, val);
+}
+
static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
@@ -520,6 +542,42 @@ static const TypeInfo pnv_chiptod_power10_type_info = {
}
};
+static int pnv_chiptod_power11_dt_xscom(PnvXScomInterface *dev, void *fdt,
+ int xscom_offset)
+{
+ const char compat[] = "ibm,power-chiptod\0ibm,power11-chiptod";
+
+ return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(compat));
+}
+
+static void pnv_chiptod_power11_class_init(ObjectClass *klass, const void *data)
+{
+ PnvChipTODClass *pctc = PNV_CHIPTOD_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
+
+ dc->desc = "PowerNV ChipTOD Controller (Power11)";
+ device_class_set_props(dc, pnv_chiptod_properties);
+
+ xdc->dt_xscom = pnv_chiptod_power11_dt_xscom;
+
+ pctc->broadcast_ttype = chiptod_power11_broadcast_ttype;
+ pctc->tx_ttype_target = chiptod_power11_tx_ttype_target;
+
+ pctc->xscom_size = PNV_XSCOM_CHIPTOD_SIZE;
+}
+
+static const TypeInfo pnv_chiptod_power11_type_info = {
+ .name = TYPE_PNV11_CHIPTOD,
+ .parent = TYPE_PNV_CHIPTOD,
+ .instance_size = sizeof(PnvChipTOD),
+ .class_init = pnv_chiptod_power11_class_init,
+ .interfaces = (const InterfaceInfo[]) {
+ { TYPE_PNV_XSCOM_INTERFACE },
+ { }
+ }
+};
+
static void pnv_chiptod_reset(void *dev)
{
PnvChipTOD *chiptod = PNV_CHIPTOD(dev);
@@ -579,6 +637,7 @@ static void pnv_chiptod_register_types(void)
type_register_static(&pnv_chiptod_type_info);
type_register_static(&pnv_chiptod_power9_type_info);
type_register_static(&pnv_chiptod_power10_type_info);
+ type_register_static(&pnv_chiptod_power11_type_info);
}
type_init(pnv_chiptod_register_types);
diff --git a/include/hw/ppc/pnv_chiptod.h b/include/hw/ppc/pnv_chiptod.h
index fde569bcbfa9..466b06560a28 100644
--- a/include/hw/ppc/pnv_chiptod.h
+++ b/include/hw/ppc/pnv_chiptod.h
@@ -17,6 +17,8 @@ OBJECT_DECLARE_TYPE(PnvChipTOD, PnvChipTODClass, PNV_CHIPTOD)
DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV9_CHIPTOD, TYPE_PNV9_CHIPTOD)
#define TYPE_PNV10_CHIPTOD TYPE_PNV_CHIPTOD "-POWER10"
DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV10_CHIPTOD, TYPE_PNV10_CHIPTOD)
+#define TYPE_PNV11_CHIPTOD TYPE_PNV_CHIPTOD "-POWER11"
+DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV11_CHIPTOD, TYPE_PNV11_CHIPTOD)
enum tod_state {
tod_error = 0,
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v8 6/8] tests/powernv: Switch to buildroot images instead of op-build
2025-06-08 18:28 [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
` (4 preceding siblings ...)
2025-06-08 18:28 ` [PATCH v8 5/8] ppc/pnv: Add ChipTOD model for Power11 Aditya Gupta
@ 2025-06-08 18:28 ` Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 7/8] tests/powernv: Add PowerNV test for Power11 Aditya Gupta
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Aditya Gupta @ 2025-06-08 18:28 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin
Cc: Harsh Prateek Bora, Mahesh J Salgaonkar, Madhavan Srinivasan,
qemu-devel, qemu-ppc, Cédric Le Goater,
Frédéric Barrat
As op-build images haven't been updated from long time (and may not get
updated in future), use buildroot images provided by cedric [1].
Use existing nvme device being used in the test to mount the initrd.
Also replace the check for "zImage loaded message" to skiboot's message
when it starts the kernel: "Starting kernel at", since we are no longer
using zImage from op-build
This is required for newer processor tests such as Power11, as the
op-build kernel image is old and doesn't support Power11.
Power11 test has been added in a later patch.
[1]: https://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64le_powernv8-2025.02
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
tests/functional/test_ppc64_powernv.py | 30 ++++++++++++++------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/tests/functional/test_ppc64_powernv.py b/tests/functional/test_ppc64_powernv.py
index 685e2178ed78..2b4db1cf99b4 100755
--- a/tests/functional/test_ppc64_powernv.py
+++ b/tests/functional/test_ppc64_powernv.py
@@ -18,9 +18,14 @@ class powernvMachine(LinuxKernelTest):
good_message = 'VFS: Cannot open root device'
ASSET_KERNEL = Asset(
- ('https://archives.fedoraproject.org/pub/archive/fedora-secondary/'
- 'releases/29/Everything/ppc64le/os/ppc/ppc64/vmlinuz'),
- '383c2f5c23bc0d9d32680c3924d3fd7ee25cc5ef97091ac1aa5e1d853422fc5f')
+ ('https://github.com/legoater/qemu-ppc-boot/raw/refs/heads/main/'
+ 'buildroot/qemu_ppc64le_powernv8-2025.02/vmlinux'),
+ '6fd29aff9ad4362511ea5d0acbb510667c7031928e97d64ec15bbc5daf4b8151')
+
+ ASSET_INITRD = Asset(
+ ('https://github.com/legoater/qemu-ppc-boot/raw/refs/heads/main/'
+ 'buildroot/qemu_ppc64le_powernv8-2025.02/rootfs.ext2'),
+ 'aee2192b692077c4bde31cb56ce474424b358f17cec323d5c94af3970c9aada2')
def do_test_linux_boot(self, command_line = KERNEL_COMMON_COMMAND_LINE):
self.require_accelerator("tcg")
@@ -78,27 +83,24 @@ def test_linux_big_boot(self):
wait_for_console_pattern(self, console_pattern, self.panic_message)
wait_for_console_pattern(self, self.good_message, self.panic_message)
-
- ASSET_EPAPR_KERNEL = Asset(
- ('https://github.com/open-power/op-build/releases/download/v2.7/'
- 'zImage.epapr'),
- '0ab237df661727e5392cee97460e8674057a883c5f74381a128fa772588d45cd')
-
def do_test_ppc64_powernv(self, proc):
self.require_accelerator("tcg")
- kernel_path = self.ASSET_EPAPR_KERNEL.fetch()
+ kernel_path = self.ASSET_KERNEL.fetch()
+ initrd_path = self.ASSET_INITRD.fetch()
self.vm.set_console()
self.vm.add_args('-kernel', kernel_path,
- '-append', 'console=tty0 console=hvc0',
+ '-drive',
+ f'file={initrd_path},format=raw,if=none,id=drive0,readonly=on',
+ '-append', 'root=/dev/nvme0n1 console=tty0 console=hvc0',
'-device', 'pcie-pci-bridge,id=bridge1,bus=pcie.1,addr=0x0',
- '-device', 'nvme,bus=pcie.2,addr=0x0,serial=1234',
+ '-device', 'nvme,drive=drive0,bus=pcie.2,addr=0x0,serial=1234',
'-device', 'e1000e,bus=bridge1,addr=0x3',
'-device', 'nec-usb-xhci,bus=bridge1,addr=0x2')
self.vm.launch()
self.wait_for_console_pattern("CPU: " + proc + " generation processor")
- self.wait_for_console_pattern("zImage starting: loaded")
- self.wait_for_console_pattern("Run /init as init process")
+ self.wait_for_console_pattern("INIT: Starting kernel at ")
+ self.wait_for_console_pattern("Run /sbin/init as init process")
# Device detection output driven by udev probing is sometimes cut off
# from console output, suspect S14silence-console init script.
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v8 7/8] tests/powernv: Add PowerNV test for Power11
2025-06-08 18:28 [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
` (5 preceding siblings ...)
2025-06-08 18:28 ` [PATCH v8 6/8] tests/powernv: Switch to buildroot images instead of op-build Aditya Gupta
@ 2025-06-08 18:28 ` Aditya Gupta
2025-06-08 18:28 ` [PATCH v8 8/8] MAINTAINERS: Add myself as a reviewer of PowerNV emulation Aditya Gupta
2025-06-23 8:23 ` [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
8 siblings, 0 replies; 10+ messages in thread
From: Aditya Gupta @ 2025-06-08 18:28 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin
Cc: Harsh Prateek Bora, Mahesh J Salgaonkar, Madhavan Srinivasan,
qemu-devel, qemu-ppc, Cédric Le Goater,
Frédéric Barrat
With all Power11 support in place, add Power11 PowerNV test.
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
tests/functional/test_ppc64_powernv.py | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/tests/functional/test_ppc64_powernv.py b/tests/functional/test_ppc64_powernv.py
index 2b4db1cf99b4..9ada832b7816 100755
--- a/tests/functional/test_ppc64_powernv.py
+++ b/tests/functional/test_ppc64_powernv.py
@@ -116,5 +116,9 @@ def test_powernv10(self):
self.set_machine('powernv10')
self.do_test_ppc64_powernv('P10')
+ def test_powernv11(self):
+ self.set_machine('powernv11')
+ self.do_test_ppc64_powernv('Power11')
+
if __name__ == '__main__':
LinuxKernelTest.main()
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v8 8/8] MAINTAINERS: Add myself as a reviewer of PowerNV emulation
2025-06-08 18:28 [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
` (6 preceding siblings ...)
2025-06-08 18:28 ` [PATCH v8 7/8] tests/powernv: Add PowerNV test for Power11 Aditya Gupta
@ 2025-06-08 18:28 ` Aditya Gupta
2025-06-23 8:23 ` [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
8 siblings, 0 replies; 10+ messages in thread
From: Aditya Gupta @ 2025-06-08 18:28 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin
Cc: Harsh Prateek Bora, Mahesh J Salgaonkar, Madhavan Srinivasan,
qemu-devel, qemu-ppc, Cédric Le Goater,
Frédéric Barrat
Proposing myself as a reviewer in the PowerNV emulation in QEMU
Have been working on PowerNV QEMU for sometime, with contributions in
Power11, MPIPL and minor fixes and things such as dtb support
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa6763077ea8..a61c8d6b203a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1564,6 +1564,7 @@ F: tests/functional/test_ppc64_tuxrun.py
PowerNV (Non-Virtualized)
M: Nicholas Piggin <npiggin@gmail.com>
R: Frédéric Barrat <fbarrat@linux.ibm.com>
+R: Aditya Gupta <adityag@linux.ibm.com>
L: qemu-ppc@nongnu.org
S: Odd Fixes
F: docs/system/ppc/powernv.rst
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v8 0/8] Power11 support for QEMU [PowerNV]
2025-06-08 18:28 [PATCH v8 0/8] Power11 support for QEMU [PowerNV] Aditya Gupta
` (7 preceding siblings ...)
2025-06-08 18:28 ` [PATCH v8 8/8] MAINTAINERS: Add myself as a reviewer of PowerNV emulation Aditya Gupta
@ 2025-06-23 8:23 ` Aditya Gupta
8 siblings, 0 replies; 10+ messages in thread
From: Aditya Gupta @ 2025-06-23 8:23 UTC (permalink / raw)
To: Cédric Le Goater, Nicholas Piggin
Cc: Harsh Prateek Bora, Mahesh J Salgaonkar, Madhavan Srinivasan,
qemu-devel, qemu-ppc
Hello,
Ping. Any comments on the series ? This doesn't have any code changes
from v6, other than fixing merge conflicts on rebase to upstream.
Thanks,
- Aditya G
On 25/06/08 11:58PM, Aditya Gupta wrote:
> Overview
> ============
>
> Note: No changes from v7, fixed minor merge conflicts on rebase.
>
> Add support for Power11 powernv machine type.
>
> As Power11 core is same as Power10, hence much of the code has been reused
> from Power10.
>
> Split Powernv11 chip/machine code into commits introducing: chip,machine,xive,phb
> This is to try to keep the code smaller in each commit, but can squash the
> xive/phb commits into respective chip/machine commit
>
> Power11 PSeries already added in QEMU in:
> commit 273db89bcaf4 ("ppc/pseries: Add Power11 cpu type")
>
> Note: Also added a patch proposing myself as a reviewer.
>
> Git Tree for Testing
> ====================
>
> QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-powernv-v8
>
> Has been tested with following cases:
> * '-M powernv' / '-M powernv10' / '-M powernv11'
> * '-smp' option tested
>
> skiboot with Power11 support: https://github.com/open-power/skiboot, since
> commit 785a5e3
>
> Linux with Power11 support: https://github.com/torvalds/linux, since v6.9-rc1
>
> Changelog
> =========
> v8:
> + rebase to upstream
> + propose myself as a powernv reviewer
>
> v7 (https://lore.kernel.org/qemu-devel/20250327200738.1524401-1-adityag@linux.ibm.com/):
> + use Power10 models of homer, sbe, occ, psi, lpc. As they are same.
> + switch powernv tests to use buildroot images instead of op-build images
> + add functional test for powernv11
> - remove dynamic sysbus device for PHBs, so no more dynamic number of
> PHBs in Power11 as it became complex to handle it and not much used
>
> v6 (https://lore.kernel.org/qemu-devel/20250325112319.927190-1-adityag@linux.ibm.com/):
> + make Pnv11Chip's parent as PnvChip, instead of Pnv10Chip
> + rebase on upstream/master
>
> v5 (https://lore.kernel.org/qemu-devel/57ce8d50-db92-44f0-96a9-e1297eea949f@kaod.org/):
> + add chiptod
> + add instance_init for P11 to use P11 models
> + move patch introducing Pnv11Chip to the last
> + update skiboot.lid to skiboot's upstream/master
>
> v4:
> + patch #5: fix memory leak in pnv_chip_power10_quad_realize
> - no change in other patches
>
> v3:
> + patch #1: version power11 as power11_v2.0
> + patch #2: split target hw/pseries code into patch #2
> + patch #3,#4: fix regression due to Power10 and Power11 having same PCR
> + patch #5: create pnv_chip_power11_dt_populate and split pnv_chip_power10_common_realize as per review
> + patch #6-#11: no change
> - remove commit to make Power11 as default
>
> v2:
> + split powernv patch into homer,lpc,occ,psi,sbe
> + reduce code duplication by reusing power10 code
> + make power11 as default
> + rebase on qemu upstream/master
> + add more information in commit descriptions
> + update docs
> + update skiboot.lid
>
>
> Aditya Gupta (8):
> ppc/pnv: Introduce Pnv11Chip
> ppc/pnv: Introduce Power11 PowerNV machine
> ppc/pnv: Add XIVE2 controller to Power11
> ppc/pnv: Add PHB5 PCIe Host bridge to Power11
> ppc/pnv: Add ChipTOD model for Power11
> tests/powernv: Switch to buildroot images instead of op-build
> tests/powernv: Add PowerNV test for Power11
> MAINTAINERS: Add myself as a reviewer of PowerNV emulation
>
> MAINTAINERS | 1 +
> docs/system/ppc/powernv.rst | 9 +-
> hw/ppc/pnv.c | 546 +++++++++++++++++++++++++
> hw/ppc/pnv_chiptod.c | 59 +++
> hw/ppc/pnv_core.c | 17 +
> include/hw/ppc/pnv.h | 38 ++
> include/hw/ppc/pnv_chip.h | 7 +
> include/hw/ppc/pnv_chiptod.h | 2 +
> include/hw/ppc/pnv_xscom.h | 49 +++
> tests/functional/test_ppc64_powernv.py | 34 +-
> 10 files changed, 744 insertions(+), 18 deletions(-)
>
> --
> 2.49.0
>
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