From: Ben Dooks <ben.dooks@codethink.co.uk>
To: nazar.kazakov@codethink.co.uk, joseph.baker@codethink.co.uk,
fran.redondo@codethink.co.uk, lawrence.hunter@codethink.co.uk,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, alistair.francis@wdc.com,
qemu-riscv@nongnu.org
Cc: ben.dooks@codethink.co.uk, qemu-devel@nongnu.org
Subject: RISC-V: Add CVA6 machine
Date: Mon, 9 Jun 2025 14:17:28 +0100 [thread overview]
Message-ID: <20250609131731.1464616-1-ben.dooks@codethink.co.uk> (raw)
Add the CVA6 (the corev_apu from the fpga) model from
https://github.com/openhwgroup/cva6
Tree at:
https://gitlab.com/CodethinkLabs/qemu/-/tree/bjdooks/cva6-send-8jun2025?ref_type=heads
Fixes:
v3:
- fix missing file source
- set 64bit only for now
v2:
- rebased and fixed whitespace issues
next reply other threads:[~2025-06-09 13:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-09 13:17 Ben Dooks [this message]
2025-06-09 13:17 ` [PATCH v3 1/3] hw/riscv: add CVA6 machine Ben Dooks
2025-06-09 23:29 ` Alistair Francis
2025-06-09 13:17 ` [PATCH v3 2/3] target/riscv: add cva6 core type Ben Dooks
2025-06-09 23:30 ` Alistair Francis
2025-06-09 13:17 ` [PATCH v3 3/3] hw/riscv: set cva6 to use TYPE_RISCV_CPU_CVA6 Ben Dooks
2025-06-09 23:30 ` Alistair Francis
-- strict thread matches above, loose matches on Subject: below --
2025-09-19 17:12 RISC-V: Add CVA6 machine Ben Dooks
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