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Mon, 09 Jun 2025 14:17:32 +0100 From: Ben Dooks To: nazar.kazakov@codethink.co.uk, joseph.baker@codethink.co.uk, fran.redondo@codethink.co.uk, lawrence.hunter@codethink.co.uk, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, alistair.francis@wdc.com, qemu-riscv@nongnu.org Cc: ben.dooks@codethink.co.uk, qemu-devel@nongnu.org Subject: [PATCH v3 2/3] target/riscv: add cva6 core type Date: Mon, 9 Jun 2025 14:17:30 +0100 Message-Id: <20250609131731.1464616-3-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.37.2.352.g3c44437643 In-Reply-To: <20250609131731.1464616-1-ben.dooks@codethink.co.uk> References: <20250609131731.1464616-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=srv_ts003@codethink.com; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.097, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add TYPE_RISCV_CPU_CVA6 for the CVA6 core Signed-off-by: Ben Dooks --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 1ee05eb393..3daf75568c 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -34,6 +34,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_CVA6 RISCV_CPU_TYPE_NAME("cva6") #define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i") #define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e") #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 629ac37501..fca45dc9d9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3009,6 +3009,17 @@ static const TypeInfo riscv_cpu_type_infos[] = { .misa_mxl_max = MXL_RV64, ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_CVA6, TYPE_RISCV_VENDOR_CPU, + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVS | RVU, + .misa_mxl_max = MXL_RV64, + .cfg.max_satp_mode = VM_1_10_SV39, + .priv_spec = PRIV_VERSION_1_12_0, + .cfg.pmp = true, + .cfg.mmu = true, + .cfg.ext_zifencei = true, + .cfg.ext_zicsr = true, + ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E, .misa_mxl_max = MXL_RV64 ), -- 2.37.2.352.g3c44437643