qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Zhenzhong Duan" <zhenzhong.duan@intel.com>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 21/24] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class
Date: Tue, 10 Jun 2025 14:56:30 +0200	[thread overview]
Message-ID: <20250610125633.24411-22-philmd@linaro.org> (raw)
In-Reply-To: <20250610125633.24411-1-philmd@linaro.org>

From: Zhenzhong Duan <zhenzhong.duan@intel.com>

RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed
parent class, class_init on them may corrupt their parent class
fields.

It's lucky that parent_realize and parent_phases are not initialized
or used until now, so just remove the definitions. They can be added
back when really necessary.

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250606092406.229833-6-zhenzhong.duan@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/riscv/iommu.h   | 6 ++----
 hw/riscv/riscv-iommu-pci.c | 6 ------
 hw/riscv/riscv-iommu-sys.c | 6 ------
 3 files changed, 2 insertions(+), 16 deletions(-)

diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h
index b03339d75ce..8a8acfc3f07 100644
--- a/include/hw/riscv/iommu.h
+++ b/include/hw/riscv/iommu.h
@@ -30,14 +30,12 @@ typedef struct RISCVIOMMUState RISCVIOMMUState;
 typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
 
 #define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci"
-OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PCI)
+OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
 typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
-typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass;
 
 #define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device"
-OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SYS)
+OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
 typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
-typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass;
 
 #define FDT_IRQ_TYPE_EDGE_LOW 1
 
diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c
index 1f44eef74ea..cdb4a7a8f03 100644
--- a/hw/riscv/riscv-iommu-pci.c
+++ b/hw/riscv/riscv-iommu-pci.c
@@ -68,12 +68,6 @@ typedef struct RISCVIOMMUStatePci {
     RISCVIOMMUState  iommu;   /* common IOMMU state */
 } RISCVIOMMUStatePci;
 
-struct RISCVIOMMUPciClass {
-    /*< public >*/
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
 /* interrupt delivery callback */
 static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector)
 {
diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
index 74e76b94a5c..e34d00aef64 100644
--- a/hw/riscv/riscv-iommu-sys.c
+++ b/hw/riscv/riscv-iommu-sys.c
@@ -53,12 +53,6 @@ struct RISCVIOMMUStateSys {
     uint8_t *msix_pba;
 };
 
-struct RISCVIOMMUSysClass {
-    /*< public >*/
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
 static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
                                      unsigned size)
 {
-- 
2.49.0



  parent reply	other threads:[~2025-06-10 13:05 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-10 12:56 [PULL 00/24] Misc HW patches for 2025-06-10 Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 01/24] hw/char/sh_serial: Delete fifo_timeout_timer in DeviceUnrealize Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 02/24] hw/char/sh_serial: Convert to TypeInfo Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 03/24] hw/pci-host/raven: Remove is-legacy-prep property Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 04/24] hw/pci-host/raven: Revert "raven: Move BIOS loading from board code to PCI host" Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 05/24] hw/core/resetcontainer: Consolidate OBJECT_DECLARE_SIMPLE_TYPE Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 06/24] hw/hyperv/balloon: Consolidate OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 07/24] hw/ppc/e500: Move clock and TB frequency to machine class Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 08/24] hw/net/fsl_etsec: Set default MAC address Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 09/24] hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal resources Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 10/24] pc-bios: ensure installed ROMs don't have execute permissions Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 11/24] MAINTAINERS: Update Akihiko Odaki's affiliation Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 12/24] tests/functional: Add a test for the Arduino UNO machine Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 13/24] accel/hvf: Fix TYPE_HVF_ACCEL instance size Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 14/24] hw/core/cpu: Move CacheType to general cpu.h Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 15/24] hw/gpio/pca9552: Avoid using g_newa() Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 16/24] backends/tpm: Avoid using g_alloca() Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 17/24] tests/unit/test-char: " Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 18/24] hw/virtio/virtio-mem: Fix definition of VirtIOMEMClass Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 19/24] hw/virtio/virtio-pmem: Fix definition of VirtIOPMEMClass Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 20/24] hw/gpio/aspeed: Fix definition of AspeedGPIOClass Philippe Mathieu-Daudé
2025-06-10 12:56 ` Philippe Mathieu-Daudé [this message]
2025-06-10 12:56 ` [PULL 22/24] hw/misc/stm32_rcc: Fix stm32_rcc_write() arguments order Philippe Mathieu-Daudé
2025-07-01 10:31   ` Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 23/24] hw/net/i82596: Update datasheet URL Philippe Mathieu-Daudé
2025-06-10 12:56 ` [PULL 24/24] hw/net/i82596: Factor configure function out Philippe Mathieu-Daudé
2025-06-11 18:22 ` [PULL 00/24] Misc HW patches for 2025-06-10 Stefan Hajnoczi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250610125633.24411-22-philmd@linaro.org \
    --to=philmd@linaro.org \
    --cc=alistair.francis@wdc.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=qemu-devel@nongnu.org \
    --cc=zhenzhong.duan@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).