Re: [PATCH v1 1/3] hw/net/can: CTU CAN FD IP core mapping to the platform bus

[Pavel Pisa <pisa@fel.cvut.cz>]

Hello Peter,

thanks for the response.

On Thursday 12 of June 2025 17:50:20 Peter Maydell wrote:
> On Wed, 28 May 2025 at 12:50, Pavel Pisa <pisa@cmp.felk.cvut.cz> wrote:
> > The system/platform bus mapping alternative to PCI/PCIe mapping.
> > In this case, the platform bus is used to match FPGA design
> > for Xilinx Zynq MZ_APO education kit with four CTU CAN FD
> > cores on branch mz_apo-2x-xcan-4x-ctu of repo
> >
> >   https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
> >
> > The system is started by command
> >
> >   qemu-system-arm -m 1G -M xilinx-zynq-a9 \
> >       -kernel kernel-zynq \
> >       -dtb zynq-microzed-uart1-2x-xcan-4x-ctu-axi.dtb \
> >       -initrd ramdisk.cpio \
> >       -serial null -serial mon:stdio \
> >       -nographic \
> >       -object can-bus,id=canbus0-bus \
> >       -object
> > can-host-socketcan,if=can0,canbus=canbus0-bus,id=canbus0-socketcan \
> > -device
> > ctucan_mm,iobase=0x43c30000,irqnum=29,irqctrl=/machine/unattached/device[
> >3],canbus=canbus0-bus \ -device
> > ctucan_mm,iobase=0x43c70000,irqnum=30,irqctrl=/machine/unattached/device[
> >3],canbus=canbus0-bus \ -device
> > ctucan_mm,iobase=0x43bf0000,irqnum=31,irqctrl=/machine/unattached/device[
> >3],canbus=canbus0-bus \ -device
> > ctucan_mm,iobase=0x43bb0000,irqnum=32,irqctrl=/machine/unattached/device[
> >3],canbus=canbus0-bus
>
> Please don't use the platform bus for this. Command line
> created devices should not have properties like "iobase"
> and should not be mapping their own MMIO regions in their
> realize methods.
>
> If we have a board that does or should have a memory-mapped
> CAN device, then that board should create it at the appropriate
> address and wire up the interrupt lines.

That is easy when SoC has integrated IP on the silicon,
in our case ESP32-C5. So if Espressif's chips are emulated
by mainline QEMU one day are, then it would be easy to add
CTU CAN FD support into appropriate chips.

My student has defended thesis documenting his FlexCAN
for iMX6 emulation last week
  https://dspace.cvut.cz/bitstream/handle/10467/122654/F3-BP-2025-Bobek-Matyas-BP_Bobek_FlexCAN_final_4.pdf
  https://gitlab.fel.cvut.cz/bobekmat/qemu-flexcan
The code will need review and there could be problems
but there are no doubts how to integrate it into QEMU
supported SoC.

But CTU CAN FD as FPGA IP component is another case.

> We don't have infrastructure currently for users to create
> custom "frankenstein" setups on the command line, and I don't
> want us to add small disconnected portions of it ad-hoc.
>
> I'll let the Zynq board maintainers make the call about whether
> they want to add a CAN bus controller to it.

I do not expect that they want it as the standard component
of the SoC support. The CTU CAN FD is an IP core which
can be synthesized from our VHDL sources
  https://canbus.pages.fel.cvut.cz/
into one of AXI processor system (PS) to programmable
logic (PL/FPGA) regions.

The Xilinx QEMU fork adds support for that with some mechanism
based on device-tree and dynamic mapping of designed IP cores
functional emulation into address space. But that is part
of their fork. I would like to support, contribute and provide
mainline QEMU to Linux, RTEMS and NuttX communities and proposed
solution seems to me as the least intrusive option.

The QEMU use is for CAN subsystem maintenance, development and
CI tests for these systems as well as the option for application
developers to test whole system including CAN communication.
We want to use it even for RTEMS, Linux and NuttX CAN testing
on PolarFife, where we plan to work even on design example
for FPGA soon.

Is there some other alternative how to add support
of FPGA AXI mapped IP cores to QEMU mainline?
If not, is there chance that something else emerges and is
acceptable in some foreseen future?

Best wishes,

                Pavel
--
                Pavel Pisa
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    e-mail:     pisa@cmp.felk.cvut.cz
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