qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
	<linuxarm@huawei.com>
Cc: <qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>,
	<eric.auger@redhat.com>, <peter.maydell@linaro.org>,
	<jgg@nvidia.com>, <nicolinc@nvidia.com>, <ddutile@redhat.com>,
	<berrange@redhat.com>, <imammedo@redhat.com>,
	<nathanc@nvidia.com>, <mochs@nvidia.com>, <smostafa@google.com>,
	<wangzhou1@hisilicon.com>, <jiangkunkun@huawei.com>,
	<jonathan.cameron@huawei.com>, <zhangfei.gao@linaro.org>
Subject: Re: [PATCH v4 2/7] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build
Date: Mon, 16 Jun 2025 11:32:50 +0100	[thread overview]
Message-ID: <20250616113236.00007fa4@huawei.com> (raw)
In-Reply-To: <20250613144449.60156-3-shameerali.kolothum.thodi@huawei.com>

On Fri, 13 Jun 2025 15:44:44 +0100
Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> wrote:

> Introduces a new struct AcpiIortSMMUv3Dev to hold all the information
> required for SMMUv3 IORT node and use that for populating the node.
> 
> The current machine wide SMMUv3 is named as legacy SMMUv3 as we will
> soon add support for user-creatable SMMUv3 devices. These changes will
> be useful to have common code paths when we add that support.
> 
> Tested-by: Nathan Chen <nathanc@nvidia.com>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Some trivial stuff inline. Otherwise only comment in passing is that
some of the loop nests are deep enough that it might be worth
considering factoring some of those out as helper functions.

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> ---
>  hw/arm/virt-acpi-build.c | 111 +++++++++++++++++++++++++++------------
>  hw/arm/virt.c            |   1 +
>  include/hw/arm/virt.h    |   1 +
>  3 files changed, 79 insertions(+), 34 deletions(-)
> 
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 7e8e0f0298..d39506179a 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -266,6 +266,36 @@ static int iort_idmap_compare(gconstpointer a, gconstpointer b)
>      return idmap_a->input_base - idmap_b->input_base;
>  }
>  
> +struct AcpiIortSMMUv3Dev {
> +    int irq;
> +    hwaddr base;
> +    GArray *idmaps;
> +    /* Offset of the SMMUv3 IORT Node relative to the start of the IORT. */
> +    size_t offset;
> +};
> +typedef struct AcpiIortSMMUv3Dev AcpiIortSMMUv3Dev;

Hmm. This file is a bit inconsistent on style but there are instances of the more
compact

typedef struct AcpiIortSMMUv3Dev {
    int irq;
    hwaddr base;
    GArray *idmaps;
    /* Offset of the SMMUv3 IORT Node relative to the start of the IORT. */
    size_t offset;
} AcpiIortSMMUv3Dev;

> +
> +static void
> +populate_smmuv3_legacy_dev(GArray *sdev_blob)
What Nicolin said here.


> +{
> +    VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine());
> +    AcpiIortSMMUv3Dev sdev;
> +
> +    sdev.idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
> +    object_child_foreach_recursive(object_get_root(),
> +                                   iort_host_bridges, sdev.idmaps);

Not sure why this wrap. I'd move iort_host_bridges up a line probably.

> +
> +    /*
> +     * There will be only one legacy SMMUv3 as it is a machine wide one.
> +     * And since it covers all the PCIe RCs in the machine, may have
> +     * multiple SMMUv3 idmaps. Sort it by input_base.
> +     */
> +    g_array_sort(sdev.idmaps, iort_idmap_compare);

I'd add a blank line here to make it more clear the comment only (I think)
applies to the one line of code and not this whole block.

> +    sdev.base = vms->memmap[VIRT_SMMU].base;
> +    sdev.irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
> +    g_array_append_val(sdev_blob, sdev);
> +}




  parent reply	other threads:[~2025-06-16 10:33 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-13 14:44 [PATCH v4 0/7] hw/arm/virt: Add support for user creatable SMMUv3 device Shameer Kolothum via
2025-06-13 14:44 ` [PATCH v4 1/7] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association Shameer Kolothum via
2025-06-16  5:04   ` Nicolin Chen
2025-06-16 10:20   ` Jonathan Cameron via
2025-06-16 11:20     ` Shameerali Kolothum Thodi via
2025-06-17  7:49     ` Eric Auger
2025-06-17 16:52       ` Jonathan Cameron via
2025-06-17 19:11         ` Donald Dutile
2025-06-18  8:35         ` Shameerali Kolothum Thodi via
2025-06-18 10:38           ` Jonathan Cameron via
2025-06-18 16:59           ` Eric Auger
2025-06-19  7:24             ` Shameerali Kolothum Thodi via
2025-06-19  7:41               ` Eric Auger
2025-06-19  8:05                 ` Shameerali Kolothum Thodi via
2025-06-19  9:30                   ` Jonathan Cameron via
2025-06-19  9:38                     ` Jonathan Cameron via
2025-06-20 11:50                       ` Jonathan Cameron via
2025-06-13 14:44 ` [PATCH v4 2/7] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build Shameer Kolothum via
2025-06-16  5:20   ` Nicolin Chen
2025-06-16 10:32   ` Jonathan Cameron via [this message]
2025-06-17  9:09   ` Eric Auger
2025-06-13 14:44 ` [PATCH v4 3/7] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Shameer Kolothum via
2025-06-16  5:25   ` Nicolin Chen
2025-06-16 10:55   ` Jonathan Cameron via
2025-06-16 11:22     ` Shameerali Kolothum Thodi via
2025-06-17  9:21   ` Eric Auger
2025-06-13 14:44 ` [PATCH v4 4/7] hw/arm/virt: Factor out common SMMUV3 dt bindings code Shameer Kolothum via
2025-06-16 10:57   ` Jonathan Cameron via
2025-06-13 14:44 ` [PATCH v4 5/7] hw/arm/virt: Add an SMMU_IO_LEN macro Shameer Kolothum via
2025-06-16 11:02   ` Jonathan Cameron via
2025-06-16 11:26     ` Shameerali Kolothum Thodi via
2025-06-13 14:44 ` [PATCH v4 6/7] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Shameer Kolothum via
2025-06-16  5:31   ` Nicolin Chen
2025-06-16 12:31     ` Shameerali Kolothum Thodi via
2025-06-16 11:05   ` Jonathan Cameron via
2025-06-17  9:25   ` Eric Auger
2025-06-13 14:44 ` [PATCH v4 7/7] qemu-options.hx: Document the arm-smmuv3 device Shameer Kolothum via
2025-06-16  5:33   ` Nicolin Chen
2025-06-16 11:12   ` Jonathan Cameron via
2025-06-16 11:24     ` Shameerali Kolothum Thodi via
2025-06-16 17:28     ` Donald Dutile

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250616113236.00007fa4@huawei.com \
    --to=qemu-devel@nongnu.org \
    --cc=berrange@redhat.com \
    --cc=ddutile@redhat.com \
    --cc=eric.auger@redhat.com \
    --cc=imammedo@redhat.com \
    --cc=jgg@nvidia.com \
    --cc=jiangkunkun@huawei.com \
    --cc=jonathan.cameron@huawei.com \
    --cc=linuxarm@huawei.com \
    --cc=mochs@nvidia.com \
    --cc=nathanc@nvidia.com \
    --cc=nicolinc@nvidia.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=shameerali.kolothum.thodi@huawei.com \
    --cc=smostafa@google.com \
    --cc=wangzhou1@hisilicon.com \
    --cc=zhangfei.gao@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).