[PATCH v1 0/2] Support the Frequency Counter Control register for AST2700

[PATCH v1 0/2] Support the Frequency Counter Control register for AST2700

[Jamin Lin via]

v1:
- Skipping dram_init in u-boot for AST2700
- Support the Frequency Counter Control register for AST2700

Jamin Lin (2):
  hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700
  hw/misc/aspeed_scu: Support the Frequency Counter Control register for
    AST2700

 hw/misc/aspeed_scu.c  | 6 ++++++
 hw/misc/aspeed_sdmc.c | 3 +++
 2 files changed, 9 insertions(+)

-- 
2.43.0

[PATCH v1 1/2] hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700

[Jamin Lin via]

On AST2700 SoC, QEMU now sets BIT6 in VGA0 SCRATCH register to indicate
that DDR training has completed, thus skipping the dram_init().

To align with the recent U-Boot changes, where the Main Control Register's
BIT16 is checked to skip the dram_init() process, this patch sets BIT16 in
the SDMC Main Control Register at reset time.

This allows both the main U-Boot stage to correctly detect and bypass DRAM
initialization when running under QEMU.

Reference:
- QEMU: https://github.com/qemu/qemu/commit/2d082fea485ee455a70ed3e963cdf9a70f34858a
- U-Boot: https://github.com/AspeedTech-BMC/u-boot/commit/94e5435504fb0d8888f5c1bfd3fa284cdd6aaf9b

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_sdmc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index f04d9930dd..dff7cc362d 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -570,6 +570,9 @@ static void aspeed_2700_sdmc_reset(DeviceState *dev)
     /* Set ram size bit and defaults values */
     s->regs[R_MAIN_CONF] = asc->compute_conf(s, 0);
 
+    /* Skipping dram init */
+    s->regs[R_MAIN_CONTROL] = BIT(16);
+
     if (s->unlocked) {
         s->regs[R_2700_PROT] = PROT_UNLOCKED;
     }
-- 
2.43.0

Re: [PATCH v1 1/2] hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700

[Cédric Le Goater]

On 6/18/25 10:00, Jamin Lin wrote:
> On AST2700 SoC, QEMU now sets BIT6 in VGA0 SCRATCH register to indicate
> that DDR training has completed, thus skipping the dram_init().
> 
> To align with the recent U-Boot changes, where the Main Control Register's
> BIT16 is checked to skip the dram_init() process, this patch sets BIT16 in
> the SDMC Main Control Register at reset time.
> 
> This allows both the main U-Boot stage to correctly detect and bypass DRAM
> initialization when running under QEMU.
> 
> Reference:
> - QEMU: https://github.com/qemu/qemu/commit/2d082fea485ee455a70ed3e963cdf9a70f34858a
> - U-Boot: https://github.com/AspeedTech-BMC/u-boot/commit/94e5435504fb0d8888f5c1bfd3fa284cdd6aaf9b
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   hw/misc/aspeed_sdmc.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
> index f04d9930dd..dff7cc362d 100644
> --- a/hw/misc/aspeed_sdmc.c
> +++ b/hw/misc/aspeed_sdmc.c
> @@ -570,6 +570,9 @@ static void aspeed_2700_sdmc_reset(DeviceState *dev)
>       /* Set ram size bit and defaults values */
>       s->regs[R_MAIN_CONF] = asc->compute_conf(s, 0);
>   
> +    /* Skipping dram init */
> +    s->regs[R_MAIN_CONTROL] = BIT(16);
> +
>       if (s->unlocked) {
>           s->regs[R_2700_PROT] = PROT_UNLOCKED;
>       }

[PATCH v1 2/2] hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700

[Jamin Lin via]

According to the datasheet:
BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement counter.
BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished.
Firmware polls BIT[6] to determine when measurement is complete.
The flag can be cleared by writing BIT[1] to 0.

To simulate this hardware behavior in QEMU:
If BIT[1] is set to 1, BIT[6] is immediately set to 1 to avoid
firmware hanging during polling.
If BIT[1] is cleared to 0, BIT[6] is also cleared to 0 to match
hardware semantics.

The initial value of this register is initialized to 0x80, reflecting the
default value confirmed from an EVB register dump.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_scu.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 4930e00fed..11d0739108 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -176,6 +176,7 @@
 #define AST2700_SCUIO_UARTCLK_GEN       TO_REG(0x330)
 #define AST2700_SCUIO_HUARTCLK_GEN      TO_REG(0x334)
 #define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388)
+#define AST2700_SCUIO_FREQ_CNT_CTL      TO_REG(0x3A0)
 
 #define SCU_IO_REGION_SIZE 0x1000
 
@@ -1022,6 +1023,10 @@ static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset,
         s->regs[reg - 1] ^= data;
         updated = true;
         break;
+    case AST2700_SCUIO_FREQ_CNT_CTL:
+        s->regs[reg] = deposit32(s->regs[reg], 6, 1, !!(data & BIT(1)));
+        updated = true;
+        break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -1066,6 +1071,7 @@ static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = {
     [AST2700_SCUIO_UARTCLK_GEN]         = 0x00014506,
     [AST2700_SCUIO_HUARTCLK_GEN]        = 0x000145c0,
     [AST2700_SCUIO_CLK_DUTY_MEAS_RST]   = 0x0c9100d2,
+    [AST2700_SCUIO_FREQ_CNT_CTL]        = 0x00000080,
 };
 
 static void aspeed_2700_scuio_class_init(ObjectClass *klass, const void *data)
-- 
2.43.0

Re: [PATCH v1 2/2] hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700

[Cédric Le Goater]

On 6/18/25 10:00, Jamin Lin wrote:
> According to the datasheet:
> BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement counter.
> BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished.
> Firmware polls BIT[6] to determine when measurement is complete.
> The flag can be cleared by writing BIT[1] to 0.
> 
> To simulate this hardware behavior in QEMU:
> If BIT[1] is set to 1, BIT[6] is immediately set to 1 to avoid
> firmware hanging during polling.
> If BIT[1] is cleared to 0, BIT[6] is also cleared to 0 to match
> hardware semantics.
> 
> The initial value of this register is initialized to 0x80, reflecting the
> default value confirmed from an EVB register dump.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   hw/misc/aspeed_scu.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index 4930e00fed..11d0739108 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -176,6 +176,7 @@
>   #define AST2700_SCUIO_UARTCLK_GEN       TO_REG(0x330)
>   #define AST2700_SCUIO_HUARTCLK_GEN      TO_REG(0x334)
>   #define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388)
> +#define AST2700_SCUIO_FREQ_CNT_CTL      TO_REG(0x3A0)
>   
>   #define SCU_IO_REGION_SIZE 0x1000
>   
> @@ -1022,6 +1023,10 @@ static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset,
>           s->regs[reg - 1] ^= data;
>           updated = true;
>           break;
> +    case AST2700_SCUIO_FREQ_CNT_CTL:
> +        s->regs[reg] = deposit32(s->regs[reg], 6, 1, !!(data & BIT(1)));
> +        updated = true;
> +        break;
>       default:
>           qemu_log_mask(LOG_GUEST_ERROR,
>                         "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
> @@ -1066,6 +1071,7 @@ static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = {
>       [AST2700_SCUIO_UARTCLK_GEN]         = 0x00014506,
>       [AST2700_SCUIO_HUARTCLK_GEN]        = 0x000145c0,
>       [AST2700_SCUIO_CLK_DUTY_MEAS_RST]   = 0x0c9100d2,
> +    [AST2700_SCUIO_FREQ_CNT_CTL]        = 0x00000080,
>   };
>   
>   static void aspeed_2700_scuio_class_init(ObjectClass *klass, const void *data)