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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Cameron Esfahani" <dirty@apple.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Julian Armistead" <julian.armistead@linaro.org>,
	"Radoslaw Biernacki" <rad@semihalf.com>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Phil Dennis-Jordan" <phil@philjordan.eu>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Daniel P. Berrangé" <berrange@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Leif Lindholm" <leif.lindholm@oss.qualcomm.com>,
	"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	qemu-arm@nongnu.org, "Roman Bolshakov" <rbolshakov@ddn.com>,
	"Alexander Graf" <agraf@csgraf.de>
Subject: [PATCH 11/20] target/arm: Create GTimers *after* features finalized / accel realized
Date: Thu, 19 Jun 2025 15:13:10 +0200	[thread overview]
Message-ID: <20250619131319.47301-12-philmd@linaro.org> (raw)
In-Reply-To: <20250619131319.47301-1-philmd@linaro.org>

Call generic (including accelerator) cpu_realize() handlers
*before* setting @gt_cntfrq_hz default

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu.c | 65 ++++++++++++++++++++++++------------------------
 1 file changed, 33 insertions(+), 32 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c99981d88f8..102f45442a9 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1986,26 +1986,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         return;
     }
 
-    if (!cpu->gt_cntfrq_hz) {
-        /*
-         * 0 means "the board didn't set a value, use the default". (We also
-         * get here for the CONFIG_USER_ONLY case.)
-         * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
-         * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
-         * which gives a 16ns tick period.
-         *
-         * We will use the back-compat value:
-         *  - for QEMU CPU types added before we standardized on 1GHz
-         *  - for versioned machine types with a version of 9.0 or earlier
-         */
-        if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
-            cpu->backcompat_cntfrq) {
-            cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
-        } else {
-            cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
-        }
-    }
-
 #ifndef CONFIG_USER_ONLY
     /* The NVIC and M-profile CPU are two halves of a single piece of
      * hardware; trying to use one without the other is a command line
@@ -2052,7 +2032,40 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
             return;
         }
     }
+#endif
 
+    cpu_exec_realizefn(cs, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    arm_cpu_finalize_features(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+#ifndef CONFIG_USER_ONLY
+    if (!cpu->gt_cntfrq_hz) {
+        /*
+         * 0 means "the board didn't set a value, use the default". (We also
+         * get here for the CONFIG_USER_ONLY case.)
+         * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
+         * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
+         * which gives a 16ns tick period.
+         *
+         * We will use the back-compat value:
+         *  - for QEMU CPU types added before we standardized on 1GHz
+         *  - for versioned machine types with a version of 9.0 or earlier
+         */
+        if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
+            cpu->backcompat_cntfrq) {
+            cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
+        } else {
+            cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
+        }
+    }
     {
         uint64_t scale = gt_cntfrq_period_ns(cpu);
 
@@ -2073,18 +2086,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 #endif
 
-    cpu_exec_realizefn(cs, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-    arm_cpu_finalize_features(cpu, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
 #ifdef CONFIG_USER_ONLY
     /*
      * User mode relies on IC IVAU instructions to catch modification of
-- 
2.49.0



  parent reply	other threads:[~2025-06-19 13:15 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-19 13:12 [PATCH 00/20] arm: Fixes and preparatory cleanups for split-accel Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 01/20] target/arm: Remove arm_handle_psci_call() stub Philippe Mathieu-Daudé
2025-06-19 21:10   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 02/20] target/arm: Reduce arm_cpu_post_init() declaration scope Philippe Mathieu-Daudé
2025-06-19 21:10   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 03/20] target/arm: Unify gen_exception_internal() Philippe Mathieu-Daudé
2025-06-19 21:12   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 04/20] target/arm/hvf: Simplify GIC hvf_arch_init_vcpu() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 05/20] target/arm/hvf: Directly re-lock BQL after hv_vcpu_run() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 06/20] target/arm/hvf: Trace hv_vcpu_run() failures Philippe Mathieu-Daudé
2025-06-19 21:14   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 07/20] accel/hvf: Trace VM memory mapping Philippe Mathieu-Daudé
2025-06-19 22:41   ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 08/20] target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event Philippe Mathieu-Daudé
2025-06-19 21:17   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 09/20] target/arm/hvf: Correct dtb_compatible value Philippe Mathieu-Daudé
2025-06-19 21:18   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 10/20] target/arm: Restrict system register properties to system binary Philippe Mathieu-Daudé
2025-06-19 21:18   ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` Philippe Mathieu-Daudé [this message]
2025-06-19 13:13 ` [PATCH 12/20] accel: Keep reference to AccelOpsClass in AccelClass Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 13/20] accel: Introduce AccelOpsClass::cpu_target_realize() hook Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 14/20] accel/hvf: Add hvf_arch_cpu_realize() stubs Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 15/20] target/arm/hvf: Really set Generic Timer counter frequency Philippe Mathieu-Daudé
2025-06-19 21:21   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 16/20] hw/arm/virt: Only require TCG || QTest to use TrustZone Philippe Mathieu-Daudé
2025-06-19 21:22   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 17/20] hw/arm/virt: Only require TCG || QTest to use virtualization extension Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 18/20] hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 19/20] hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition Philippe Mathieu-Daudé
2025-06-19 13:36   ` Leif Lindholm
2025-06-19 21:09   ` Richard Henderson
2025-06-19 21:20     ` Philippe Mathieu-Daudé
2025-06-19 21:28       ` Richard Henderson
2025-06-19 21:34         ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 20/20] tests/functional/sbsa-ref: Move where machine type is set Philippe Mathieu-Daudé
2025-06-19 13:23   ` Philippe Mathieu-Daudé
2025-06-19 14:40     ` Leif Lindholm

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