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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Cameron Esfahani" <dirty@apple.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Julian Armistead" <julian.armistead@linaro.org>,
	"Radoslaw Biernacki" <rad@semihalf.com>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Phil Dennis-Jordan" <phil@philjordan.eu>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Daniel P. Berrangé" <berrange@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Leif Lindholm" <leif.lindholm@oss.qualcomm.com>,
	"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	qemu-arm@nongnu.org, "Roman Bolshakov" <rbolshakov@ddn.com>,
	"Alexander Graf" <agraf@csgraf.de>
Subject: [PATCH 04/20] target/arm/hvf: Simplify GIC hvf_arch_init_vcpu()
Date: Thu, 19 Jun 2025 15:13:03 +0200	[thread overview]
Message-ID: <20250619131319.47301-5-philmd@linaro.org> (raw)
In-Reply-To: <20250619131319.47301-1-philmd@linaro.org>

Only update the ID_AA64PFR0_EL1 register when a GIC is provided.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/hvf/hvf.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 42258cc2d88..06cfb7ba253 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1057,11 +1057,13 @@ int hvf_arch_init_vcpu(CPUState *cpu)
                               arm_cpu->mp_affinity);
     assert_hvf_ok(ret);
 
-    ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
-    assert_hvf_ok(ret);
-    pfr |= env->gicv3state ? (1 << 24) : 0;
-    ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
-    assert_hvf_ok(ret);
+    if (env->gicv3state) {
+        ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
+        assert_hvf_ok(ret);
+        pfr = FIELD_DP64(pfr, ID_AA64PFR0, GIC, 1);
+        ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
+        assert_hvf_ok(ret);
+    }
 
     /* We're limited to underlying hardware caps, override internal versions */
     ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
-- 
2.49.0



  parent reply	other threads:[~2025-06-19 13:15 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-19 13:12 [PATCH 00/20] arm: Fixes and preparatory cleanups for split-accel Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 01/20] target/arm: Remove arm_handle_psci_call() stub Philippe Mathieu-Daudé
2025-06-19 21:10   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 02/20] target/arm: Reduce arm_cpu_post_init() declaration scope Philippe Mathieu-Daudé
2025-06-19 21:10   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 03/20] target/arm: Unify gen_exception_internal() Philippe Mathieu-Daudé
2025-06-19 21:12   ` Richard Henderson
2025-06-19 13:13 ` Philippe Mathieu-Daudé [this message]
2025-06-19 13:13 ` [PATCH 05/20] target/arm/hvf: Directly re-lock BQL after hv_vcpu_run() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 06/20] target/arm/hvf: Trace hv_vcpu_run() failures Philippe Mathieu-Daudé
2025-06-19 21:14   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 07/20] accel/hvf: Trace VM memory mapping Philippe Mathieu-Daudé
2025-06-19 22:41   ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 08/20] target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event Philippe Mathieu-Daudé
2025-06-19 21:17   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 09/20] target/arm/hvf: Correct dtb_compatible value Philippe Mathieu-Daudé
2025-06-19 21:18   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 10/20] target/arm: Restrict system register properties to system binary Philippe Mathieu-Daudé
2025-06-19 21:18   ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 11/20] target/arm: Create GTimers *after* features finalized / accel realized Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 12/20] accel: Keep reference to AccelOpsClass in AccelClass Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 13/20] accel: Introduce AccelOpsClass::cpu_target_realize() hook Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 14/20] accel/hvf: Add hvf_arch_cpu_realize() stubs Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 15/20] target/arm/hvf: Really set Generic Timer counter frequency Philippe Mathieu-Daudé
2025-06-19 21:21   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 16/20] hw/arm/virt: Only require TCG || QTest to use TrustZone Philippe Mathieu-Daudé
2025-06-19 21:22   ` Richard Henderson
2025-06-19 13:13 ` [PATCH 17/20] hw/arm/virt: Only require TCG || QTest to use virtualization extension Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 18/20] hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 19/20] hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition Philippe Mathieu-Daudé
2025-06-19 13:36   ` Leif Lindholm
2025-06-19 21:09   ` Richard Henderson
2025-06-19 21:20     ` Philippe Mathieu-Daudé
2025-06-19 21:28       ` Richard Henderson
2025-06-19 21:34         ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 20/20] tests/functional/sbsa-ref: Move where machine type is set Philippe Mathieu-Daudé
2025-06-19 13:23   ` Philippe Mathieu-Daudé
2025-06-19 14:40     ` Leif Lindholm

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