From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Cameron Esfahani" <dirty@apple.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Julian Armistead" <julian.armistead@linaro.org>,
"Radoslaw Biernacki" <rad@semihalf.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Phil Dennis-Jordan" <phil@philjordan.eu>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Leif Lindholm" <leif.lindholm@oss.qualcomm.com>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-arm@nongnu.org, "Roman Bolshakov" <rbolshakov@ddn.com>,
"Alexander Graf" <agraf@csgraf.de>
Subject: [PATCH 06/20] target/arm/hvf: Trace hv_vcpu_run() failures
Date: Thu, 19 Jun 2025 15:13:05 +0200 [thread overview]
Message-ID: <20250619131319.47301-7-philmd@linaro.org> (raw)
In-Reply-To: <20250619131319.47301-1-philmd@linaro.org>
Allow distinguishing HV_ILLEGAL_GUEST_STATE in trace events.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/arm/hvf/hvf.c | 10 +++++++++-
target/arm/hvf/trace-events | 1 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 30dfd97bebf..1ff3ff7b91a 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1914,7 +1914,15 @@ int hvf_vcpu_exec(CPUState *cpu)
bql_unlock();
r = hv_vcpu_run(cpu->accel->fd);
bql_lock();
- assert_hvf_ok(r);
+ switch (r) {
+ case HV_SUCCESS:
+ break;
+ case HV_ILLEGAL_GUEST_STATE:
+ trace_hvf_illegal_guest_state();
+ /* fall through */
+ default:
+ g_assert_not_reached();
+ }
/* handle VMEXIT */
uint64_t exit_reason = hvf_exit->reason;
diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
index 4fbbe4b45ec..a4870e0a5c4 100644
--- a/target/arm/hvf/trace-events
+++ b/target/arm/hvf/trace-events
@@ -11,3 +11,4 @@ hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%
hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"
hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=0x%016"PRIx64"]"
hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=0x%016"PRIx64"]"
+hvf_illegal_guest_state(void) "HV_ILLEGAL_GUEST_STATE"
--
2.49.0
next prev parent reply other threads:[~2025-06-19 13:14 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-19 13:12 [PATCH 00/20] arm: Fixes and preparatory cleanups for split-accel Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 01/20] target/arm: Remove arm_handle_psci_call() stub Philippe Mathieu-Daudé
2025-06-19 21:10 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 02/20] target/arm: Reduce arm_cpu_post_init() declaration scope Philippe Mathieu-Daudé
2025-06-19 21:10 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 03/20] target/arm: Unify gen_exception_internal() Philippe Mathieu-Daudé
2025-06-19 21:12 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 04/20] target/arm/hvf: Simplify GIC hvf_arch_init_vcpu() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 05/20] target/arm/hvf: Directly re-lock BQL after hv_vcpu_run() Philippe Mathieu-Daudé
2025-06-19 13:13 ` Philippe Mathieu-Daudé [this message]
2025-06-19 21:14 ` [PATCH 06/20] target/arm/hvf: Trace hv_vcpu_run() failures Richard Henderson
2025-06-19 13:13 ` [PATCH 07/20] accel/hvf: Trace VM memory mapping Philippe Mathieu-Daudé
2025-06-19 22:41 ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 08/20] target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event Philippe Mathieu-Daudé
2025-06-19 21:17 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 09/20] target/arm/hvf: Correct dtb_compatible value Philippe Mathieu-Daudé
2025-06-19 21:18 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 10/20] target/arm: Restrict system register properties to system binary Philippe Mathieu-Daudé
2025-06-19 21:18 ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 11/20] target/arm: Create GTimers *after* features finalized / accel realized Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 12/20] accel: Keep reference to AccelOpsClass in AccelClass Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 13/20] accel: Introduce AccelOpsClass::cpu_target_realize() hook Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 14/20] accel/hvf: Add hvf_arch_cpu_realize() stubs Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 15/20] target/arm/hvf: Really set Generic Timer counter frequency Philippe Mathieu-Daudé
2025-06-19 21:21 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 16/20] hw/arm/virt: Only require TCG || QTest to use TrustZone Philippe Mathieu-Daudé
2025-06-19 21:22 ` Richard Henderson
2025-06-19 13:13 ` [PATCH 17/20] hw/arm/virt: Only require TCG || QTest to use virtualization extension Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 18/20] hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized() Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 19/20] hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition Philippe Mathieu-Daudé
2025-06-19 13:36 ` Leif Lindholm
2025-06-19 21:09 ` Richard Henderson
2025-06-19 21:20 ` Philippe Mathieu-Daudé
2025-06-19 21:28 ` Richard Henderson
2025-06-19 21:34 ` Philippe Mathieu-Daudé
2025-06-19 13:13 ` [PATCH 20/20] tests/functional/sbsa-ref: Move where machine type is set Philippe Mathieu-Daudé
2025-06-19 13:23 ` Philippe Mathieu-Daudé
2025-06-19 14:40 ` Leif Lindholm
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