From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Leif Lindholm" <leif.lindholm@oss.qualcomm.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Radoslaw Biernacki" <rad@semihalf.com>,
"Alexander Graf" <agraf@csgraf.de>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Phil Dennis-Jordan" <phil@philjordan.eu>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Bernhard Beschow" <shentey@gmail.com>,
"Cleber Rosa" <crosa@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Cameron Esfahani" <dirty@apple.com>,
kvm@vger.kernel.org, qemu-arm@nongnu.org,
"Eric Auger" <eric.auger@redhat.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Thomas Huth" <thuth@redhat.com>,
"Roman Bolshakov" <rbolshakov@ddn.com>,
"John Snow" <jsnow@redhat.com>
Subject: [PATCH v2 12/26] target/arm: Restrict system register properties to system binary
Date: Fri, 20 Jun 2025 15:06:55 +0200 [thread overview]
Message-ID: <20250620130709.31073-13-philmd@linaro.org> (raw)
In-Reply-To: <20250620130709.31073-1-philmd@linaro.org>
Do not expose the following system-specific properties on user-mode
binaries:
- psci-conduit
- cntfrq (ARM_FEATURE_GENERIC_TIMER)
- rvbar (ARM_FEATURE_V8)
- has-mpu (ARM_FEATURE_PMSA)
- pmsav7-dregion (ARM_FEATURE_PMSA)
- reset-cbar (ARM_FEATURE_CBAR)
- reset-hivecs (ARM_FEATURE_M)
- init-nsvtor (ARM_FEATURE_M)
- init-svtor (ARM_FEATURE_M_SECURITY)
- idau (ARM_FEATURE_M_SECURITY)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/arm/cpu.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index eb0639de719..e5b70f5de81 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1500,6 +1500,7 @@ static void arm_cpu_initfn(Object *obj)
* 0 means "unset, use the default value". That default might vary depending
* on the CPU type, and is set in the realize fn.
*/
+#ifndef CONFIG_USER_ONLY
static const Property arm_cpu_gt_cntfrq_property =
DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
@@ -1509,7 +1510,6 @@ static const Property arm_cpu_reset_cbar_property =
static const Property arm_cpu_reset_hivecs_property =
DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
-#ifndef CONFIG_USER_ONLY
static const Property arm_cpu_has_el2_property =
DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
@@ -1532,6 +1532,7 @@ static const Property arm_cpu_has_neon_property =
static const Property arm_cpu_has_dsp_property =
DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
+#ifndef CONFIG_USER_ONLY
static const Property arm_cpu_has_mpu_property =
DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
@@ -1544,6 +1545,7 @@ static const Property arm_cpu_pmsav7_dregion_property =
DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
pmsav7_dregion,
qdev_prop_uint32, uint32_t);
+#endif
static bool arm_get_pmu(Object *obj, Error **errp)
{
@@ -1731,6 +1733,7 @@ static void arm_cpu_post_init(Object *obj)
"Set on/off to enable/disable aarch64 "
"execution state ");
}
+#ifndef CONFIG_USER_ONLY
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
@@ -1746,7 +1749,6 @@ static void arm_cpu_post_init(Object *obj)
OBJ_PROP_FLAG_READWRITE);
}
-#ifndef CONFIG_USER_ONLY
if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
/* Add the has_el3 state CPU property only if EL3 is allowed. This will
* prevent "has_el3" from existing on CPUs which cannot support EL3.
@@ -1818,6 +1820,7 @@ static void arm_cpu_post_init(Object *obj)
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
}
+#ifndef CONFIG_USER_ONLY
if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
@@ -1854,8 +1857,6 @@ static void arm_cpu_post_init(Object *obj)
&cpu->psci_conduit,
OBJ_PROP_FLAG_READWRITE);
- qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
-
if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
}
@@ -1864,7 +1865,6 @@ static void arm_cpu_post_init(Object *obj)
kvm_arm_add_vcpu_properties(cpu);
}
-#ifndef CONFIG_USER_ONLY
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
cpu_isar_feature(aa64_mte, cpu)) {
object_property_add_link(obj, "tag-memory",
@@ -1882,6 +1882,7 @@ static void arm_cpu_post_init(Object *obj)
}
}
#endif
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
}
static void arm_cpu_finalizefn(Object *obj)
--
2.49.0
next prev parent reply other threads:[~2025-06-20 13:11 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-20 13:06 [PATCH v2 00/26] arm: Fixes and preparatory cleanups for split-accel Philippe Mathieu-Daudé
2025-06-20 13:06 ` [PATCH v2 01/26] target/arm: Remove arm_handle_psci_call() stub Philippe Mathieu-Daudé
2025-06-20 13:06 ` [PATCH v2 02/26] target/arm: Reduce arm_cpu_post_init() declaration scope Philippe Mathieu-Daudé
2025-06-20 13:06 ` [PATCH v2 03/26] target/arm: Unify gen_exception_internal() Philippe Mathieu-Daudé
2025-06-20 13:06 ` [PATCH v2 04/26] target/arm/hvf: Simplify GIC hvf_arch_init_vcpu() Philippe Mathieu-Daudé
2025-06-22 0:40 ` Richard Henderson
2025-06-20 13:06 ` [PATCH v2 05/26] target/arm/hvf: Directly re-lock BQL after hv_vcpu_run() Philippe Mathieu-Daudé
2025-06-22 0:12 ` Richard Henderson
2025-06-20 13:06 ` [PATCH v2 06/26] target/arm/hvf: Trace hv_vcpu_run() failures Philippe Mathieu-Daudé
2025-06-20 13:06 ` [PATCH v2 07/26] accel/hvf: Trace VM memory mapping Philippe Mathieu-Daudé
2025-06-22 0:12 ` Richard Henderson
2025-06-20 13:06 ` [PATCH v2 08/26] target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event Philippe Mathieu-Daudé
2025-06-20 13:06 ` [PATCH v2 09/26] target/arm: Correct KVM & HVF dtb_compatible value Philippe Mathieu-Daudé
2025-06-22 0:17 ` Richard Henderson
2025-06-20 13:06 ` [PATCH v2 10/26] accel/hvf: Model PhysTimer register Philippe Mathieu-Daudé
2025-06-22 0:40 ` Richard Henderson
2025-06-20 13:06 ` [PATCH v2 11/26] target/arm/hvf: Pass @target_el argument to hvf_raise_exception() Philippe Mathieu-Daudé
2025-06-22 0:19 ` Richard Henderson
2025-06-20 13:06 ` Philippe Mathieu-Daudé [this message]
2025-06-22 0:20 ` [PATCH v2 12/26] target/arm: Restrict system register properties to system binary Richard Henderson
2025-06-20 13:06 ` [PATCH v2 13/26] target/arm: Create GTimers *after* features finalized / accel realized Philippe Mathieu-Daudé
2025-06-22 0:22 ` Richard Henderson
2025-06-20 13:06 ` [PATCH v2 14/26] accel: Keep reference to AccelOpsClass in AccelClass Philippe Mathieu-Daudé
2025-06-20 13:06 ` [PATCH v2 15/26] accel: Introduce AccelOpsClass::cpu_target_realize() hook Philippe Mathieu-Daudé
2025-06-22 0:23 ` Richard Henderson
2025-06-20 13:06 ` [PATCH v2 16/26] accel/hvf: Add hvf_arch_cpu_realize() stubs Philippe Mathieu-Daudé
2025-06-22 0:24 ` Richard Henderson
2025-06-20 13:07 ` [PATCH v2 17/26] target/arm/hvf: Really set Generic Timer counter frequency Philippe Mathieu-Daudé
2025-06-20 13:07 ` [PATCH v2 18/26] target/arm/hvf: Trace host processor features Philippe Mathieu-Daudé
2025-06-22 0:29 ` Richard Henderson
2025-06-20 13:07 ` [PATCH v2 19/26] hw/arm/virt: Only require TCG || QTest to use TrustZone Philippe Mathieu-Daudé
2025-06-20 13:07 ` [PATCH v2 20/26] hw/arm/virt: Only require TCG || QTest to use virtualization extension Philippe Mathieu-Daudé
2025-06-20 13:07 ` [PATCH v2 21/26] hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized() Philippe Mathieu-Daudé
2025-06-22 0:30 ` Richard Henderson
2025-06-20 13:07 ` [PATCH v2 22/26] hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition Philippe Mathieu-Daudé
2025-06-22 0:34 ` Richard Henderson
2025-06-20 13:07 ` [PATCH v2 23/26] tests/functional: Restrict nexted Aarch64 Xen test to TCG Philippe Mathieu-Daudé
2025-06-22 0:35 ` Richard Henderson
2025-06-23 8:11 ` Thomas Huth
2025-06-23 11:59 ` Philippe Mathieu-Daudé
2025-06-23 12:05 ` Philippe Mathieu-Daudé
2025-06-20 13:07 ` [PATCH v2 24/26] tests/functional: Require TCG to run Aarch64 imx8mp-evk test Philippe Mathieu-Daudé
2025-06-22 0:37 ` Richard Henderson
2025-06-23 8:19 ` Thomas Huth
2025-06-23 11:54 ` Philippe Mathieu-Daudé
2025-06-20 13:07 ` [PATCH v2 25/26] tests/functional: Add hvf_available() helper Philippe Mathieu-Daudé
2025-06-22 0:38 ` Richard Henderson
2025-06-23 8:20 ` Thomas Huth
2025-06-20 13:07 ` [PATCH v2 26/26] tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator Philippe Mathieu-Daudé
2025-06-23 8:23 ` Thomas Huth
2025-06-23 11:53 ` Philippe Mathieu-Daudé
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