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From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <shiju.jose@huawei.com>
Cc: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>,
	<tanxiaofei@huawei.com>, <prime.zeng@hisilicon.com>,
	<linuxarm@huawei.com>
Subject: Re: [PATCH v2 2/7] hw/cxl/events: Updates for rev3.2 general media event record
Date: Fri, 20 Jun 2025 15:13:14 +0100	[thread overview]
Message-ID: <20250620151314.0000535c@huawei.com> (raw)
In-Reply-To: <20250619151619.1695-3-shiju.jose@huawei.com>

On Thu, 19 Jun 2025 16:16:14 +0100
<shiju.jose@huawei.com> wrote:

> From: Shiju Jose <shiju.jose@huawei.com>
> 
> CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
> table has updated with following new fields.
> 1. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 2. Corrected Memory Error Count at Event
> 3. Memory Event Sub-Type
> 
> Add updates for the above spec changes in the CXL general media event
> reporting and QMP command to inject general media event.
> 
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
This has the same constraints on not changing the qemu api stuff
in a non backwards compatible way.

So make them optional parameters and fill them in with what
we'd get if the device didn't support cme. These only really
make sense if we have memory event type 5 anyway:
Advanced Programmable Corrected Memory Counter Expiration

We don't need to enforce that in the interface though.

I don't mind if we do the incompatible 'counter expiry'
and a count of 0 for a type 5 event.  We could check for that
specific condition given the spec calls it out and reject the
injection but perhaps we are better leaving it fully flexible
so we can poke the OS with that invalid state.  Any real
test paths will set it appropriately so the counter is non 0
when we signal the event.

> ---
>  hw/mem/cxl_type3.c          |  9 +++++++++
>  hw/mem/cxl_type3_stubs.c    |  3 +++
>  include/hw/cxl/cxl_events.h |  7 +++++--
>  qapi/cxl.json               | 14 +++++++++++++-
>  4 files changed, 30 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 0787a9bfca..410ff445d0 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1813,6 +1813,7 @@ static const QemuUUID memory_module_uuid = {
>  #define CXL_GMER_VALID_RANK                             BIT(1)
>  #define CXL_GMER_VALID_DEVICE                           BIT(2)
>  #define CXL_GMER_VALID_COMPONENT                        BIT(3)
> +#define CXL_GMER_VALID_COMPONENT_ID_FORMAT              BIT(4)
>  
>  static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
>  {
> @@ -1840,6 +1841,9 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
>                                          bool has_rank, uint8_t rank,
>                                          bool has_device, uint32_t device,
>                                          const char *component_id,
> +                                        uint8_t cme_ev_flags,
> +                                        uint32_t cme_count,
> +                                        uint8_t sub_type,
>                                          Error **errp)
>  {
>      Object *obj = object_resolve_path(path, NULL);
> @@ -1898,10 +1902,15 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
>          strncpy((char *)gem.component_id, component_id,
>                  sizeof(gem.component_id) - 1);
>          valid_flags |= CXL_GMER_VALID_COMPONENT;
> +        valid_flags |= CXL_GMER_VALID_COMPONENT_ID_FORMAT;
>      }
>  
>      stw_le_p(&gem.validity_flags, valid_flags);
>  
> +    gem.cme_ev_flags = cme_ev_flags;
> +    st24_le_p(gem.cme_count, cme_count);
> +    gem.sub_type = sub_type;
> +
>      if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) {
>          cxl_event_irq_assert(ct3d);
>      }
> diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
> index 263d8b4609..b2a11bded8 100644
> --- a/hw/mem/cxl_type3_stubs.c
> +++ b/hw/mem/cxl_type3_stubs.c
> @@ -23,6 +23,9 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
>                                          bool has_rank, uint8_t rank,
>                                          bool has_device, uint32_t device,
>                                          const char *component_id,
> +                                        uint8_t cme_ev_flags,
> +                                        uint32_t cme_count,
> +                                        uint8_t sub_type,
>                                          Error **errp) {}
>  
>  void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint32_t flags,
> diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
> index 4d9cfdb621..352f9891bd 100644
> --- a/include/hw/cxl/cxl_events.h
> +++ b/include/hw/cxl/cxl_events.h
> @@ -115,10 +115,10 @@ typedef struct CXLEventInterruptPolicy {
>  
>  /*
>   * General Media Event Record
> - * CXL r3.1 Section 8.2.9.2.1.1; Table 8-45
> + * CXL r3.2 Section 8.2.10.2.1.1; Table 8-57
>   */
>  #define CXL_EVENT_GEN_MED_COMP_ID_SIZE  0x10
> -#define CXL_EVENT_GEN_MED_RES_SIZE      0x2e
> +#define CXL_EVENT_GEN_MED_RES_SIZE      0x29
>  typedef struct CXLEventGenMedia {
>      CXLEventRecordHdr hdr;
>      uint64_t phys_addr;
> @@ -130,6 +130,9 @@ typedef struct CXLEventGenMedia {
>      uint8_t rank;
>      uint8_t device[3];
>      uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
> +    uint8_t cme_ev_flags;
> +    uint8_t cme_count[3];
> +    uint8_t sub_type;
>      uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
>  } QEMU_PACKED CXLEventGenMedia;
>  
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index c38585d3c8..dd01d50c25 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -82,6 +82,16 @@
>  # @component-id: Device specific component identifier for the event.
>  #     May describe a field replaceable sub-component of the device.
>  #
> +# @cme-ev-flags: Advanced programmable corrected memory error
> +#     threshold event flags.
> +#     See CXL r3.2 Table 8-57 General Media Event Record.
> +#
> +# @cme-count: Corrected memory error count at event.
> +#     See CXL r3.2 Table 8-57 General Media Event Record.
> +#
> +# @sub-type: Memory event sub-type.
> +#     See CXL r3.2 Table 8-57 General Media Event Record.
> +#
>  # Since: 8.1
>  ##
>  { 'command': 'cxl-inject-general-media-event',
> @@ -91,7 +101,9 @@
>              'dpa': 'uint64', 'descriptor': 'uint8',
>              'type': 'uint8', 'transaction-type': 'uint8',
>              '*channel': 'uint8', '*rank': 'uint8',
> -            '*device': 'uint32', '*component-id': 'str' } }
> +            '*device': 'uint32', '*component-id': 'str',
> +            'cme-ev-flags':'uint8', 'cme-count':'uint32',
> +            'sub-type':'uint8' } }
>  
>  ##
>  # @cxl-inject-dram-event:



  reply	other threads:[~2025-06-20 14:14 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-19 15:16 [PATCH v2 0/7] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features shiju.jose--- via
2025-06-19 15:16 ` [PATCH v2 1/7] hw/cxl/events: Update for rev3.2 common event record format shiju.jose--- via
2025-06-20 14:03   ` Jonathan Cameron via
2025-06-24  9:10     ` Shiju Jose via
2025-06-19 15:16 ` [PATCH v2 2/7] hw/cxl/events: Updates for rev3.2 general media event record shiju.jose--- via
2025-06-20 14:13   ` Jonathan Cameron via [this message]
2025-06-19 15:16 ` [PATCH v2 3/7] hw/cxl/events: Updates for rev3.2 DRAM " shiju.jose--- via
2025-06-19 15:16 ` [PATCH v2 4/7] hw/cxl/events: Updates for rev3.2 memory module " shiju.jose--- via
2025-06-19 15:16 ` [PATCH v2 5/7] hw/cxl/cxl-mailbox-utils: Move declaration of scrub and ECS feature attributes in cmd_features_set_feature() shiju.jose--- via
2025-06-20 14:16   ` Jonathan Cameron via
2025-06-19 15:16 ` [PATCH v2 6/7] hw/cxl: Add Maintenance support shiju.jose--- via
2025-06-20 14:40   ` Jonathan Cameron via
2025-06-19 15:16 ` [PATCH v2 7/7] hw/cxl: Add emulation for memory sparing control feature shiju.jose--- via
2025-06-20 14:48   ` Jonathan Cameron via

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